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PDF WM8192 Data sheet ( Hoja de datos )
| Número de pieza | WM8192 | |
| Descripción | (8+8) Bit Output 16-bit CIS/CCD AFE/Digitiser | |
| Fabricantes | Wolfson Microelectronics plc | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de WM8192 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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WM8192
(8 + 8) Bit Output 16-bit CIS/CCD AFE/Digitiser
Product Preview, June 2000, Rev 1.0
DESCRIPTION
The WM8192 is a 16-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 6MSPS.
The device includes three analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset adjust functions. Three multiplexers allow single
channel processing. The output from each of these
channels is time multiplexed into a single high-speed 16-bit
Analogue to Digital Converter. The digital output data is
available in 8 or 4-bit wide multiplexed format.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
signals. An external reference level may also be supplied.
ADC references are generated internally, ensuring optimum
performance from the device.
Using an analogue supply voltage of 5V and a digital
interface supply of either 5V or 3.3V, the WM8192 typically
only consumes 240mW when operating from a single
5V supply.
FEATURES
• 16-bit ADC
• 6MSPS conversion rate
• Low power – 240mW typical
• 5V single supply or 5V/3.3V dual supply operation
• Single or 3 channel operation
• Correlated double sampling
• Programmable gain (8-bit resolution)
• Programmable offset adjust (8-bit resolution)
• Programmable clamp voltage
• 8 or 4-bit wide multiplexed data output formats
• Internally generated voltage references
• 28-pin SOIC package
• Serial control interface
APPLICATIONS
• Flatbed and sheetfeed scanners
• USB compatible scanners
• Multi-function peripherals
• High-performance CCD sensor interface
BLOCK DIAGRAM
VRLC/VBIAS
(26)
VSMP MCLK
(5) (7)
AVDD DVDD1 DVDD2
(21) (3) (10)
VRT VRX VRB
(24) (25) (23)
RINP (1)
GINP (28)
BINP (27)
CL
RLC
RLC
RS VS
M
U
X
TIMING CONTROL
CDS
RM
GU
X
B
8
OFFSET
DAC
VREF/BIAS
+ PGA
RM
GU
X
B
I/P SIGNAL
8 POLARITY
ADJUST
CDS
+ PGA
8 OFFSET
DAC
8 I/P SIGNAL
POLARITY
ADJUST
+
M
+U
X
WM8192
16-
BIT
ADC
DATA
I/O
PORT
(4) OEB
(13) OP[0]
(14) OP[1]
(15) OP[2]
(16) OP[3]
(17) OP[4]
(18) OP[5]
(19) OP[6]
(20) OP[7]/SDO
RLC
RLC 4
DAC
CDS
+ PGA
+
8 OFFSET
DAC
8 I/P SIGNAL
POLARITY
ADJUST
CONFIGURABLE
SERIAL
CONTROL
INTERFACE
(9) SEN
(12) SCK
(11) SDI
(6) RLC/ACYC
(22)
AGND1
(2)
AGND2
(8)
DGND
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: [email protected]
http://www.wolfson.co.uk
Product Preview data sheets contain
specifications for products in the formative
phase of development. These products may
be changed or discontinued without notice.
2000 Wolfson Microelectronics Ltd.
1 page  
Product Preview
WM8192
Test Conditions
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated.
PARAMETER
SYMBOL
Programmable Gain Amplifier
Resolution
Gain
Max gain, each channel
Min gain, each channel
Gain error, each channel
DIGITAL SPECIFICATIONS
Digital Inputs
High level input voltage
Low level input voltage
High level input current
Low level input current
Input capacitance
Digital Outputs
High level output voltage
Low level output voltage
High impedance output current
Digital IO Pins
Applied high level input voltage
Applied low level input voltage
High level output voltage
Low level output voltage
Low level input current
High level input current
Input capacitance
High impedance output current
Supply Currents
Total supply current − active
Total analogue supply current −
active
Digital core supply current,
DVDD1 − active
Digital I/O supply current,
DVDD2 − active
Supply current − full power down
mode
GMAX
GMIN
VIH
VIL
IIH
IIL
CI
VOH
VOL
IOZ
VIH
VIL
VOH
VOL
IIL
IIH
CI
IOZ
IAVDD
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
8
208
283 − PGA[7 : 0]
7.4
0.74
1
bits
V/V
V/V
V/V
%
IOH = 1mA
IOL = 1mA
IOH = 1mA
IOL = 1mA
0.8 ∗ DVDD2
V
0.2 ∗ DVDD2 V
1 µA
1 µA
5 pF
DVDD2 - 0.5
V
0.5 V
1 µA
0.8 ∗ DVDD2
V
0.2 ∗ DVDD2 V
DVDD2 - 0.5
V
0.5 V
1 µA
1 µA
5 pF
1 µA
48 mA
45 mA
2 mA
1 mA
100 µA
WOLFSON MICROELECTRONICS LTD
PP Rev 1.0 June 2000
5
5 Page 
Product Preview
WM8192
The INPUT SAMPLING BLOCK produces an effective input voltage V1. For CDS, this is the
difference between the input video level VIN and the input reset level VRESET. For non-CDS this is the
difference between the input video level VIN and the voltage on the VRLC/VBIAS pin, VVRLC,
optionally set via the RLC DAC.
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the
black level of the input signal towards 0V, producing V2.
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,
outputting voltage V3.
The ADC BLOCK then converts the analogue signal, V3, to a 16-bit unsigned digital output, D1.
The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D2.
CALCULATING OUTPUT FOR ANY GIVEN INPUT
The following equations describe the processing of the video and reset level signals through
the WM8192.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, VRESET, is subtracted from the
input video.
V1 =
VIN - VRESET .................................................................. Eqn. 1
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted
instead.
V1 =
VIN - VVRLC .................................................................... Eqn. 2
If RLCEXT = 1, VVRLC is an externally applied voltage on pin VRLC/VBIAS.
If RLCEXT = 0, VVRLC is the output from the internal RLC DAC.
VVRLC =
(VRLCSTEP ∗ RLCV[3:0]) + VRLCBOT ................................. Eqn. 3
VRLCSTEP is the step size of the RLC DAC and VRLCBOT is the minimum output of the RLC DAC.
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V1 is added to the Offset DAC output.
V2 =
V1 + {260mV ∗ (DAC[7:0]-127.5) } / 127.5 .................... Eqn. 4
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain,
V3 =
V2 ∗ 208/(283- PGA[7:0]) .............................................. Eqn. 5
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 16-bit unsigned number, with input range configured by
PGAFS[1:0].
D1[15:0] = INT{ (V3 /VFS) ∗ 65535} + 32767 PGAFS[1:0] = 00 or 01 ..... Eqn. 6
D1[15:0] = INT{ (V3 /VFS) ∗ 65535}
PGAFS[1:0] = 11 .............. Eqn. 7
D1[15:0] = INT{ (V3 /VFS) ∗ 65535} + 65535 PGAFS[1:0] = 10 .............. Eqn. 8
where the ADC full-scale range, VFS = 3V
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP.
D2[15:0] = D1[15:0]
D2[15:0] = 61535 – D1[15:0]
(INVOP = 0) ...................... Eqn. 9
(INVOP = 1) ...................... Eqn. 10
WOLFSON MICROELECTRONICS LTD
PP Rev 1.0 June 2000
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet WM8192.PDF ] | |
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