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PDF WM8190 Data sheet ( Hoja de datos )
| Número de pieza | WM8190 | |
| Descripción | (8+6) Bit Output 14-bit CIS/CCD AFE/Digitiser | |
| Fabricantes | Wolfson Microelectronics plc | |
| Logotipo |  |
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WM8190
(8 + 6) Bit Output 14-bit CIS/CCD AFE/Digitiser
Advanced Information, August 1999, Rev 3.0
DESCRIPTION
The WM8190 is a 14-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 6MSPS.
The device includes three analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset adjust functions. Three multiplexers allow single
channel processing. The output from each of these
channels is time multiplexed into a single high-speed 14-bit
Analogue to Digital Converter. The digital output data is
available in 8, 7 or 4-bit wide multiplexed format, with no
missing codes.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
signals. An external reference level may also be supplied.
ADC references are generated internally, ensuring optimum
performance from the device.
Using an analogue supply voltage of 5V and a digital
interface supply of either 5V or 3.3V, the WM8190 typically
only consumes 250mW when operating from a single
5V supply.
FEATURES
• 14-bit ADC
• No missing codes guaranteed
• 6MSPS conversion rate
• Low power – 250mW typical
• 5V single supply or 5V/3.3V dual supply operation
• Single or 3 channel operation
• Correlated double sampling
• Programmable gain (8-bit resolution)
• Programmable offset adjust (8-bit resolution)
• Programmable clamp voltage
• 8,7 or 4-bit wide multiplexed data output formats
• Internally generated voltage references
• 28-pin SOIC package
• Serial control interface
APPLICATIONS
• Flatbed and sheetfeed scanners
• USB compatible scanners
• Multi-function peripherals
• High-performance CCD sensor interface
BLOCK DIAGRAM
VRLC/VBIAS
(26)
VSMP MCLK
(5) (7)
AVDD DVDD1 DVDD2
(21) (3) (10)
VRT VRX VRB
(24) (25) (23)
RINP (1)
GINP (28)
BINP (27)
CL
RLC
RLC
RS VS
M
U
X
TIMING CONTROL
CDS
RM
GU
X
B
8
OFFSET
DAC
+ PGA
RM
GU
X
B
8
VREF/BIAS
I/P SIGNAL
POLARITY
ADJUST
CDS
+ PGA
8 OFFSET
DAC
8 I/P SIGNAL
POLARITY
ADJUST
+
M
+U
X
WM8190
14-
BIT
ADC
DATA
I/O
PORT
(4) OEB
(13) OP[0]
(14) OP[1]
(15) OP[2]
(16) OP[3]
(17) OP[4]
(18) OP[5]
(19) OP[6]
(20) OP[7]/SDO
RLC
RLC 4
DAC
CDS
+ PGA
+
8 OFFSET
DAC
8 I/P SIGNAL
POLARITY
ADJUST
CONFIGURABLE
SERIAL
CONTROL
INTERFACE
(9) SEN
(12) SCK
(11) SDI
(6) RLC/ACYC
(22)
AGND1
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: [email protected]
http://www.wolfson.co.uk
(2)
AGND2
(8)
DGND
Advanced Information data sheets contain
preliminary data on new products in the
preproduction phase of development.
Supplementary data will be published at a
later date.
©1999 Wolfson Microelectronics Ltd.
1 page  
Advanced Information
WM8190
Test Conditions
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated.
PARAMETER
Programmable Gain Amplifier
Resolution
Gain
Max gain, each channel
Min gain, each channel
Gain error, each channel
DIGITAL SPECIFICATIONS
Digital Inputs
High level input voltage
Low level input voltage
High level input current
Low level input current
Input capacitance
Digital Outputs
High level output voltage
Low level output voltage
High impedance output current
Digital IO Pins
Applied high level input voltage
Applied low level input voltage
High level output voltage
Low level output voltage
Low level input current
High level input current
Input capacitance
High impedance output current
Supply Currents
Total supply current − active
Total analogue supply current −
active
Digital core supply current,
DVDD1 − active
Digital I/O supply current,
DVDD2 − active
Supply current − full power down
mode
SYMBOL
GMAX
GMIN
VIH
VIL
IIH
IIL
CI
VOH
VOL
IOZ
VIH
VIL
VOH
VOL
IIL
IIH
CI
IOZ
IAVDD
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
8
208
283 − PGA[7 : 0]
7.4
0.74
1
bits
V/V
V/V
V/V
%
IOH = 1mA
IOL = 1mA
IOH = 1mA
IOL = 1mA
0.8 ∗ DVDD2
V
0.2 ∗ DVDD2 V
1 µA
1 µA
5 pF
DVDD2 - 0.5
V
0.5 V
1 µA
0.8 ∗ DVDD2
V
0.2 ∗ DVDD2 V
DVDD2 - 0.5
V
0.5 V
1 µA
1 µA
5 pF
1 µA
50 mA
47 mA
2 mA
1 mA
100 µA
WOLFSON MICROELECTRONICS LTD
AI Rev 3.0 August 1999
5
5 Page 
Advanced Information
WM8190
MCLK
VSMP
VS
RS/CL (CDSREF = 00)
RS/CL (CDSREF = 01)
RS/CL (CDSREF = 10)
RS/CL (CDSREF = 11)
Figure 9 Reset Sample and Clamp Timing
For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed
with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described
above. The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this
mode.
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset for each
channel are independently programmable by writing to control bits DAC[7:0] and PGA[7:0].
In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order
(Red → Green → Blue → Red…) by pulsing the ACYC/RLC pin, or controlled via the FME,
ACYCNRLC and INTM[1:0] bits. Refer to the Line-by-Line Operation section for more details.
ADC INPUT BLACK LEVEL ADJUST
The output from the PGA must be offset to match the full-scale range of the ADC. For negative-going
input signals, a black level (zero differential) output from the PGA should be offset to the top of the
ADC range. For positive going input signal the black level should be offset to the bottom of the ADC
range. This is achieved by writing to control bits PGAFS[1:0].
OVERALL SIGNAL FLOW SUMMARY
Figure 10 represents the processing of the video signal through the WM8190.
INPUT
SAMPLING OFFSET DAC PGA
BLOCK
BLOCK BLOCK
V1 V2 V3
- XVIN + + +
analog
CDS = 1
VRESET
CDS = 0
PGA gain
A = 208/(283-PGA[7:0])
ADC BLOCK
x (16383/V FS)
+0 if PGAFS[1:0]=11
+16383 if PGAFS[1:0]=10
+8191 if PGAFS[1:0]=0x
OUTPUT
INVERT
BLOCK
D1
digital
TO MULTI-
PLEXER FOR
8-BIT OUTPUT
D2
OP[13:0]
D2 = D1 if INVOP = 0
D2 = 16383-D1 if INVOP = 1
VVRLC
RLCEXT=1 RLCEXT=0
Offset 260mV*(DAC[7:0]-127.5)/127.5
DAC
VIN is RINP or GINP or BINP
VRESET is VIN sampled during reset clamp
VVRLC is voltage applied to VRLC pin
RLC
DAC V RLCSTEP*RLCV[3:0] + VRLCBOT
CDS, RLCEXT,RLCV[3:0], DAC[7:0],
PGA[7:0], PGAFS[1:0] and INVOP are set
by programming internal control registers.
CDS=1 for CDS, 0 for non-CDS
Figure 10 Overall Signal Flow
WOLFSON MICROELECTRONICS LTD
AI Rev 3.0 August 1999
11
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet WM8190.PDF ] | |
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