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PDF WM8148 Data sheet ( Hoja de datos )
| Número de pieza | WM8148 | |
| Descripción | 12-bit/12MSPS CCD/CIS Analogue Front End/Digitiser | |
| Fabricantes | Wolfson Microelectronics plc | |
| Logotipo |  |
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WM8148
12-bit/12MSPS CCD/CIS Analogue Front End/Digitiser
Production Data, April 1999, Rev 4.0
DESCRIPTION
The WM8148 is a 12-bit, 12MSPS analogue front end/
digitiser IC, which interfaces to colour or monochrome linear
array CCDs or contact image sensors (CIS). The device
includes all the signal conditioning circuitry required to
process the analogue signals from the CCD or CIS prior to
the internal ADC.
Three signal-processing channels are included in the
device. Each channel features reset level clamping,
correlated double sampling (CDS), offset correction and
programmable gain amplification (PGA). The output signal
from each channel is then multiplexed into a high
performance 12-bit analogue to digital converter (ADC).
The reset level clamp and/or CDS functions can be selected
or bypassed depending on the application.
The WM8148 can be operated in several modes. The
operational mode of the device, including the sampling
scheme and power management is programmed via the
serial/parallel control interface.
Output data is presented in either 12-bit parallel or byte-
wide (8+4-bit) format.
FEATURES
• Correlated double sampling
• Programmable gain amplifier
• Programmable input clamp voltage
• Offset correction
• 12-bit, 12MSPS ADC
• Internal voltage reference
• 12-bit or 8+4 bit data output mode
• Single 5V supply or 5V analogue/3.3V digital supply
• Programmable sample timing
• Control interface compatible with previous Wolfson
AFEs
• 48-pin TQFP package
APPLICATIONS
• Flatbed scanners
• Document scanners
• Multi-function peripherals (MFPs)
• Colour copiers
• Character recognition systems
• Linear array CCDs
• Contact image sensors (CIS)
BLOCK DIAGRAM
RLC MCLK VSMP
(2) (5) (7)
AVDD 1- 4
(41,28,27,3)
DVDD1-2
(1,13)
VRX VRB VRT
(32) (29) (31)
CL RS VS
TIMING CONTROL
VREF/BIAS
WM8148
RINP (36)
GINP (37)
BINP (39)
VRLC (33)
CDS
RLC
CDS
RLC
CDS
RLC
RLC 4
DAC
8 OFFSET
DAC
+ PGA
6 SC±AFLUELL_..2
+
8
OFFSET
DAC
+ PGA
6 SC±AFLUELL_..2
+ MUX
12-BIT
ADC
12/8
BIT
MUX
8
OFFSET
DAC
+ PGA
6 SC±AFLUELL_..2
+
CONFIGURABLE
SERIAL/PARALLEL
CONTROL INTERFACE
(35,40,30,25,6)
AGND1 - 5
(8,24,4,26)
DGND1 - 4
(43) OEB
OP[11:0]
(9-12,14-21)
(48) PNS
(34) OVRD
(45) SDI/DNA
(46) SCK/RNW
(47) SEN/STB
(42) NRESET
(44) SDO
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: [email protected]
http://www.wolfson.co.uk
Production Data contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics' Terms and Conditions.
©1999 Wolfson Microelectronics Ltd.
1 page  
WM8148
Production Data
ELECTRICAL CHARACTERISTICS
TEST CONDITIONS
AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 48MHz unless
otherwise stated (AVDD denotes the voltage applied to all AVDD pins).
PARAMETER
SYMBOL
TEST
CONDITIONS
MIN
Overall System Performance Including 12-bit ADC, PGA, Offset and CDS Functions
NO MISSING CODES GUARANTEED
Full-scale input voltage range
Max Gain
Gain = 1.0
Min Gain
Zero-scale transition error
Gain = 1.0
Full-scale transition error
Gain = 1.0
Differential non-linearity
DNL
Gain = 1.0
Integral non-linearity
INL Gain = 1.0
ANALOGUE SPECIFICATION
Input Multiplexer
Channel to channel gain matching
Input voltage range
References
VIN
0
Upper reference voltage
VRT
3.00
Lower reference voltage
VRB
1.50
Input return bias voltage
VRX
1.50
Diff. reference voltage (VRT-VRB)
VRTB
1.30
Output resistance VRT, VRB, VRX
VRT, VRB, VRX
buffers enabled
Resistance VRT to VRB
VRT, VRB buffers
disabled
500
VRX Hi-Z leakage current
VRX buffer disabled
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC Hi-Z leakage current
VRLC = 0 to AVDD
VRLC DAC resolution
4
VRLC DAC step
AVDD = 5V
290
VRLC short-circuit current
VRLC output resistance
VRLC = AVDD
VRLC = 0V
VRLC = other
Offset DAC
Resolution
8
Differential non-linearity
DNL
-0.25
Integral non-linearity
INL
-0.50
Output voltage
Code 00(hex)
Code FF(hex)
Programmable Gain Amplifier. Monotonicity Guaranteed
Resolution
6
Max gain, each channel
GMAX
Min gain, each channel
GMIN
Gain error, each channel
TYP
0.413
3.0
4.13
20
20
0.25
1.0
1
3.30
1.80
1.75
1.50
2
800
75
333
5
80
80
5
0.05
0.10
-200
200
7.4
0.74
2
MAX
UNIT
1.00
V
V
V
mV
mV
LSB
LSB
AVDD
3.60
2.10
2.00
1.70
1100
1
1
370
0.25
0.50
5
%
V
V
V
V
V
Ω
Ω
µA
Ω
µA
bits
mV/step
mA
Ω
Ω
Ω
bits
LSB
LSB
mV
mV
bits
V/V
V/V
%
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
5
5 Page 
WM8148
SERIAL INTERFACE
tSPER
SCK
SDI
tSSU
tSH
SEN
SDO
tSCKL tSCKH
tSCE
tSEW tSEC
tSESD
tSCSD
Production Data
tSCSDZ
Figure 7 Serial Interface Timing
TEST CONDITIONS
AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 48MHz unless
otherwise stated (AVDD denotes the voltage applied to all AVDD pins).
PARAMETER
SCK period
SCK high
SCK low
SDI set-up time
SDI hold time
SCK to SEN set-up time
SEN to SCK set-up time
SEN pulse width
SEN low to SDO out
SCK low to SDO out
SCK low to SDO high impedance
SYMBOL
tSPER
tSCKH
tSCKL
tSSU
tSH
tSCE
tSEC
tSEW
tSESD
tSCSD
tSCSDZ
TEST CONDITIONS
MIN
83.3
20
20
10
10
20
20
50
TYP
MAX
35
35
25
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: Parameters are measured at 50% of the rising/falling edge.
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
11
11 Page | ||
| Páginas | Total 43 Páginas | |
| PDF Descargar | [ Datasheet WM8148.PDF ] | |
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