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PDF WL102BC Data sheet ( Hoja de datos )

Número de pieza WL102BC
Descripción Wireless Data Controller
Fabricantes Mitel Networks Corporation 
Logotipo Mitel Networks Corporation Logotipo



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No Preview Available ! WL102BC Hoja de datos, Descripción, Manual

Features
q Complete CMOS, single chip, radio transceiver
controller
q Hardware implemented Communication Control
Block (CCB)
q Protocol independent design using external flash
memory
q Internal 8051 and external processor options
q Internal/external buffer and processor RAM
q Block power down facility
q PCMCIA/8bit processor host interface to buffer
RAM
q Up to 1Mbps/2 level or 2 Mbps/4 level operation
WL102B
Wireless Data Controller
Advance Information
DS4582 - 3.0 July 1999
Ordering Information
WL102B/IG/TP1R 100 pin package
WL102BC/PR/FP1R 144 pin package
The WL102B is a highly integrated CMOS wireless data
controller designed to dramatically reduce the cost of
radio data applications. It works with the WL600C RF IF
chip and WL800 synthesiser chip to offer a complete
solution for a frequency hopping, spread spectrum radio
in the 2.4 to 2.45GHz ISM band.
Its flexible design means that it can also be used in a
wide range of other applications using a range of "proc-
essor", protocols and additional memory options as well
as radios at other frequencies.
Related Documents
WL600C, WL800 and WL102B (DS4837) Datasheets
Receive
Transmit
Status
Control
Address
Data
Control
Communications
Control Block
DMA
Buffer RAM
6K4
Memory Control Block
Interrupt
Address
Data
Control
Port Pins
Interrupt
8051
System RAM
4K
Counters
Power Down
Control
Attribute
Memory
WL102
Figure 1 WL102 Minimum configuration block diagram
Configuration

1 page




WL102BC pdf
Advance Information
WL102
Memory Control Block
The memory Control Block allows access to the dual port
buffer used to communicate between the Host and WL102
system processes. The control logic of the buffer RAM
allows the Host to asynchronously read or write data at the
same time as the WL102 MAC system. To help arbitrate
access to this buffer space, a hardware semaphore
system is also included.
The WL102 contains 6784 bytes of low power buffer RAM
on chip. The 144-pin package option also allows for an
external (single port) SRAM to be used to increase the
buffer RAM space, up to 64Kbytes.
Host Interface
The Host Interface has been designed to be flexible
enough to allow its use from small microprocessor systems
to PC-Card slots. In a minimum configuration it uses only
4 address locations and a standard microprocessor type
read and write cycle. The interface provides access to the
Buffer RAM, which is accessible by both the Host and the
MAC systems simultaneously, and also to a control regis-
ter which allows the Host to reset or interrupt the MAC
processor, and performs some other control functions on
the WL102.
Packets of data are typically buffered in the internal buffer
RAM before being transmitted or transferred from the MAC
system to the host.
The 8-bit interface is microprocessor and PCMCIA-com-
patible, with a separate dedicated RAM providing 255
bytes of attribute memory used for the configuration and
control of a PC Card. The host interface may be used by
any microprocessor-type interface which can supply two
bits of address, a chip enable signal, read/write strobes
and 8 bits of data, subject to timing requirements of the
WL102. The interface also provides an interrupt signalling
mechanism between the Host and MAC system as well as
some other control functions, such as a hardware sema-
phore and reset circuitry.
Communications Control Block
This block of the WL102 performs many of the functions
required for transmission and reception of data packets,
and interfaces directly to the radio transceiver. For power
sensitive applications the configuration registers can have
their clocks switched off once the initial configuration is
complete and for protocols which allow the transceiver to
sleep for periods of time, the clocks to the entire block can
be disabled via the Power Control register.
The CCB handles all the control signals for the radio and
can be configured for the timing required by the transceiver
being used. The CCB can directly access data stored in the
buffer RAM, via a DMA bus separate to the processor bus,
and once configured will finally handle a transmission or
reception, including CRC checking, address match, op-
tional data scrambling (Bias suppression encoding) and
transfer of the data to/from the buffer RAM.
For shorter network management packets the MAC
system processor can directly read/write up to 64 bytes of
data from/to the CCB FIFO. The CCB generates maskable
interrupts to the MAC system processor at defined points
in the receive/transmit process to allow the processor to
perform any additional processing required to
succcccessfully complete the receive or transmit
sequence.
The Features of the CCB include:
q Transmission and reception of 2-level and 4-level
GFSK
bit streams at 625Kbps, 1Mbps and 2Mbps.
q Configurable Preamble/Frame word generation
and recognition
q Checksum generation and validation (CRC-16 and
CRC-32)
q Optional data coding schemes: bit-stuffing,
scrambling and bias suppression encoding (as
per draft IEEE 802.11)
q Dedicated data path for DMA transfer to and from
buffer RAM
q Address matching on received data packet
q Analysis of received signal for performing clear
channel assessment, including 16-bit countdown
timer
q 8 (maskable) interrupt sources to optimise
operation of the system software
q Automatic synthesiser channel loading for Rx/Tx
when using WL600/WL800
5

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