DataSheet.es    


PDF PCF8831 Data sheet ( Hoja de datos )

Número de pieza PCF8831
Descripción STN RGB - 160 output row driver
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



Hay una vista previa y un enlace de descarga de PCF8831 (archivo pdf) en la parte inferior de esta página.


Total 28 Páginas

No Preview Available ! PCF8831 Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
PCF8831
STN RGB - 160 output row driver
Preliminary specification
2002 Aug 14

1 page




PCF8831 pdf
Philips Semiconductors
STN RGB - 160 output row driver
Preliminary specification
PCF8831
6 PINNING
SYMBOL
R159 to R0
RCLK
PAD(1)
2 to 161
187
RP 188
FI 189
SVM
190
ROWRES1
191
ROWRES2
192
R1F
SW1
SW2
193
194
195
T1 to T5
VSS
VDD
VM
VMH
VH
VL
196 to 200
201 to 207
208 to 214
215 to 221
222 to 228
229 to 235
236 to 242
TYPE
O
I
I
I
I
I
I
I
I
I
I
PS
PS
PS
PS
PS
PS
DESCRIPTION
LCD row outputs
clock input to the shift register; data is transmitted with the positive clock
edge; connect RCLK to the RCLK output of the PCF8832 column driver
row pulse input; driven by the RP output of the PCF8832 column driver
frame inversion input; controls frame and N-line inversion; FI is synchronized
internally by the rising edge of RCLK; FI can change only when RP changes;
connect FI to the FI output of the PCF8832 column driver
input that switches the non-selected level (VM or VSS, depending on
ROWRES2) to all row outputs; connect SVM to the SVM output of the
PCF8832 column driver
external reset input 1; when LOW, the shift register is reset at the next rising
edge of RCLK and all outputs (R0 to R159) go to their non-selected level;
connect ROWRES1 to the RESROW output of the PCF8832 column driver
external reset input 2; when LOW, the non-selected level goes to VSS; when
HIGH, the non-selected level goes to VM; connect ROWREST to the
RESROW output of the PCF8832 column driver
inputs R1F (row block 1 first), SW1 (swap row block 1) and SW2 (swap row
block 2) control the shift direction through the register and the order of the
register; see Table 1; connect to the corresponding signal outputs of the
PCF8832 column driver, or connect directly to VDD or VSS as required by the
display module configuration
test inputs; connect to VSS for normal operation
logic power supply, negative; normally connected to system ground
logic power supply, positive; 2.4 to 3.5 V referred to VSS
MID-level LCD driving voltage; level is between VH and VL; output at rows for
non-selecting periods when ROWRES2 is HIGH; 1.25 to 2.0 V referred to VSS
auxiliary supply voltage for row switch; higher than VM; limited at VL + 40 V
HIGH-level LCD driving voltage; top level of the positive selecting pulse of row
outputs
LOW-level LCD driving voltage; bottom level of the negative selecting pulse of
row outputs
Note
1. Dummy pads are located at positions 1 (slanted), 162 to 186 and 243 to 272.
2002 Aug 14
5

5 Page





PCF8831 arduino
Philips Semiconductors
STN RGB - 160 output row driver
Preliminary specification
PCF8831
10 DC CHARACTERISTICS
(VDD VSS) = 2.4 to 3.5 V; (VH VL) = 15 to 55 V; Tamb = 40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
VL LOW-level LCD driving
voltage
VH HIGH-level LCD driving
voltage
VM MID-level LCD driving
voltage
CONDITIONS
MIN.
TYP.
0
VL + 15.0
VSS -V----L----+2-----V----H--
MAX.
UNIT
V
VL + 45.0 V
VDD
V
VMH
VSS
VDD
VIH
VIL
ILI
RO
IDD
IVH
IVMH
IVM
IVL
auxiliary supply voltage for
row switching
logic supply negative
voltage
logic supply positive voltage
HIGH-level input voltage all inputs; referred to VSS
LOW-level input voltage
all inputs; referred to VSS
input leakage current
row output on-state
resistance
current at pad VDD
current at pad VH
current at pad VMH
current at pad VM
current at pad VL
all inputs
VI = VDD
VI = VSS
notes 2 and 3
IO = +100 µA
IO = ±100 µA
IO = 100 µA
notes 3, 4 and 5
note 1
VM + 10
VM 2.0
VSS + 2.4
VSS + 0.8 ×
(VDD VSS)
VSS
−−
5
600
600
600
30
10
3
2
13
VL + 40
V
VM 1.25 V
VSS + 3.5
VDD
V
V
VSS + 0.2 × V
(VDD VSS)
5 µA
− µA
tbf
tbf
tbf
tbf µA
tbf µA
tbf µA
tbf µA
tbf µA
Notes
1. The minimum level of (VMH VM) depends on (VM VL); a lower level of (VM VL) requires lower offset of VMH
referred to VM. A higher level of (VMH VM) improves dynamic behaviour. A minimum level of
(VMH VM) = 2.5 V + 0.2 × (VM VL) should be maintained.
2. Row outputs tested one at a time.
3. (VH VL) = 37 V; VMH = VH; (VDD VSS) = 2.8 V; VM = -V----H----2-+----V-----L- ; (VM VSS) = 1.47 V.
4. fRCLK = 19.2 kHz; SVM = 0; ROWRES1 = ROWRES2 = HIGH; single line mode; all row outputs open-circuit.
5. Frame inversion frequency fFI = 2---f--R×----C-1--L--6K---0-- .
2002 Aug 14
11

11 Page







PáginasTotal 28 Páginas
PDF Descargar[ Datasheet PCF8831.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
PCF8831STN RGB - 160 output row driverNXP Semiconductors
NXP Semiconductors
PCF8831USTN RGB - 160 output row driverNXP Semiconductors
NXP Semiconductors
PCF8833STN RGB - 132 X 132 X 3 driverNXP Semiconductors
NXP Semiconductors
PCF88331STN RGB - 132 X 132 X 3 driverNXP Semiconductors
NXP Semiconductors

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar