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PDF W89C940 Data sheet ( Hoja de datos )
| Número de pieza | W89C940 | |
| Descripción | ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH PCI INTERFACE) | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W89C940
ELANC-PCI (TWISTED-PAIR ETHER-LAN CONTROLLER WITH
PCI INTERFACE)
GENERAL DESCRIPTION
he ELANC-PCI (Twisted-pair Ether-LAN Controller with PCI Interface) integrates a W89C902 Serial(ELANC-
PCI) LAN Coprocessor for Twisted-Pair (SLCT) and PC/AT PCI bus interface logic into a single chip. The
ELANC-PCI provides an easy way of implementing the interface between an IEEE 802.3-compatible Ethernet
and a personal computer, ELANC-PCI also provide fast DMA operation to improve the packet transmit and
receive performance.
The PCI bus is a high performance local bus architecture with low latency random access time. It is a
synchronous bus with operation up to 33MHz. The PCI bus interface is designed to provide the registers with
the device information required for configuration, recording the status of the lines , control registers, interrupt
line and I/O base address registers. It is capable of functioning in a half-duplex environment.
The W89C940Fis designed to fully comply with the standard of PCI 2.0 specification. Taking advantage of PCI's
nature, W89C940F supports auto-configuration function to free users' depression and confusion on tunning
system resources conflict. With extremely high throughput on PCI bus, W89C940F offers a 32 bits data path to
highly boost its performance without extra cost. Comparing with LAN card with ISA bus, its improvement is
excellent. Besides, it also supports up to 256KB flash memory reserved for various applications, for instance
anti-virus, popular drivers, Boot ROM, viewing your PC assets...etc., and what is more, these software are able
to be updated on line. This can increase more niche feature on your LAN card, help you get more and bright
your company profile. W89C940F is a single chip - build-in PCI bus interface and all necessary circuits - which
will let design and board assembly become easy.
FEATURES
• Fully compatible with IEEE 802.3 standard
• Software compatible with Novell NE2000
• Complies with PCI Local Bus Specification Revision 2.0
• Slave Mode for PCI bus
• Fast DMA operation enhancing network access performance
• AUI, UTP interface available
• Supports one chip 32Kx8 and 16Kx8 SRAM
• Supports up to 64KB boot ROM
• EEPROM auto-load function after power on reset
• EEPROM on-board programming function available
• UTP interface polarity auto detection correction function available
• UTP/BNC auto media-switching function provided
• LED displaying for network segment Link/activity status
• Signature register available for device identification
• Single 5V power supply with low power consumption
• 100 Pin PQFP
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W89C940
NAME
IRDY#
NUMBER
11
TRDY#
12
STOP#
IDSEL
14
98
DEVSEL#
INTA#
13
88
TYPE
s/t/s
in
s/t/s
s/t/s
in
s/t/s
o/d
PCI INTERFACE
DESCRIPTION
Initiator Ready:
Initiator Ready indicates the host's ability to complete the current data phase of
transaction. During a write cycle, IRDY# indicates that valid data is presented on
AD[31:00]. During a read cycle, it indicates the master is ready to accept the
data. The wait cycles are inserted till IRDY# and TRDY# are asserted at the
same cycle.
Target Ready:
Target Ready indicates the W89C940's ability to complete the current data phase
of transaction. During a read cycle, TRDY# indicates that valid data is presented
on AD[31:00]. During a write cycle, it indicates the W89C940 is ready to accept
the data. The wait cycles are inserted till both IRDY# and TRDY# are asserted at
the same cycle.
STOP:
Stop indicates W89C940 is requesting the master to stop the current transaction.
Initialization Device Select:
IDSEL is used as a chip select during PCI configuration read and write
transaction.
Device Select:
DEVSEL# will be asserted when W89C940 decode the correct address.
Interrupt Request:
INTA# is used to request an interrupt service. The interrupt signal can be
masked by the register of IMR( Interrupt Mask Register). INTA# status is kept at
ISR( Interrupt Status Register).
NAME
X1
X2
TXP
TXN
NUMBER
53
52
75
74
TYPE
I/TTL
O/TTL
O/AUI
NETWORK INTERFACE
DESCRIPTION
Crystal or Oscillator Input.
Crystal or oscillator input (X1) and output (X2) pin. If a crystal is used, it should
be connected directly to X1 and X2. If an oscillator is selected, X1 is the 20 MHz
input and X2 should be left floating.
AUI Transmit Output:
AUI differential output pair. The data transmitted by DTE will be sent through TXP
and TXN in a differential signal with manchest code format. A 270 ohm pull-down
resistor is required for each of TXP and TXN. TXP and TXN should be isolated
by a pulse transformer from directly connecting outside loop.
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W89C940
File 1
The ELANC-PCI also contains a Serial Network Adapter (SNA), which adapts the Non-Return-to-Zero (NRZ)
used in the core processor and host system to Manchester coded network symbols.
The SNA contains three blocks: a Phase Locked Loop (PLL), a Manchester encoder/decoder, and a collision
decoder, as well as crystal/oscillator logic.
The Manchester encoder/decoder handles code interpretation between NRZ signals and Manchester coded
signals. The PLL locks the receiving signals with an internal voltage control oscillator (VCO) so that network
noise(jitter) can be eliminated before the signals enter the core coprocessor. The collision decoder detects
whether the network is in a collision status.
10BASE-T MAU FUNCTION
TP Transceiver Operation
Transmit Driver
There are two signals for data transmission, TXP and TXN, which connect to the twisted-pair cable via a
transmitter filter and an optional common mode choke.
Smart Squelch
The main function of this block is to determine when valid data are present on the differential receiving inputs
(RXP/RXN). To ensure that impulse noise on the medium will not be taken as a valid datum, this circuit adopts
a combination of amplitude and timing measurements to determine the validity of the input signals. To qualify
incoming data, the smart squelch circuitry monitors the signals for three peaks of alternating polarity that occur
within a 400 nS window. Once this condition has been satisfied, the squelch level is reduced to minimize the
noise effect and the chances of causing premature Start Of Idle (SOI) pulse detection. If the receiver detects
activity on the receive line while packets are being transmitted, incoming data is qualified on five peaks of
alternating polarity so as to prevent false collisions caused by impulse noise. The squelch function returns to its
squelch state under any of the following conditions:
− A normal Start Of Idle (SOI) signal
− An inverted SOI signal
− A missing SOI signal
A missing SOI signal is assumed when no transitions have occurred on the receiver for 175nS after a packet
has arrived. In this case, a normal SOI signal is generated and appended to the data.
Collision Detection
A collision occurs when transmit and receive signals occur simultaneously on the twisted pair cable. Collisions
will not be reported when the device is in link-fail state. The collision signal is also generated when the
transceiver has detected a jabber condition or when the SQE test is being performed.
SQE test
The Signal Quality Error (SQE) test is used to test the collision signaling circuitry in the Twisted Pair
Transceiver module. After each packet transmission, an SQE signal is sent to the SLCT. The SLCT expects this
signal and will flag an error if it does not exist.
Jabber
The jabber timer monitors the transmitter and disables the transmission if the transmitter is active for greater
than 26.2 mS.The jabber will re-enable the transmitter after the SLCT has been idle for at least 420 mS.
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