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PDF W83L518D Data sheet ( Hoja de datos )
| Número de pieza | W83L518D | |
| Descripción | Integrated Media Reader | |
| Fabricantes | Winbond | |
| Logotipo |  |
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Winbond
Integrated Media Reader
W83L518D
Datasheet
1 page  
W83L518D
2 FUNCTIONS
2.1 General
q LPC bus is compliant with LPC Spec. 1.01
q LPC bus supports LDRQ# (LPC DMA), SERIRQ (serial IRQ)
q Programmable configuration settings
q 48 MHz crystal inputs
q PCICLK of 33 MHz is needed for LPC bus configuration
2.2 Smart Card Interface
q ISO-7816 compliant
q PC/SC T=0, T=1 compliant
q 16-byte transmitter FIFO and 16-byte receiver FIFO
q FIFO threshold interrupt to optimize system performance
q Programmable transmission clock frequency
q Versatile baud rate configuration
q UART-like register file structure
q General-purpose C4, C8 channels
2.3 Memory Stick Interface
q Memory Stick Standard Format Specifications ver. 1.3 compliant
q Support interrupt polling transmission
q Support FIFO threshold interrupt to optimize system performance
q Automatic clock halt to prevent underrun/overrun
q 16 MHz interface clock
2.4 SD Memory Card Interface
q SD Memory Card Specifications: Part 1 PHYSICAL LAYER SPECIFICATION Version 1.0 Compliant
q Support interrupt polling transmission
q Support FIFO threshold interrupt to leverage system performance
q 24 MHz interface clock
2.5 Package
q 48-pin LQFP
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation
The trademarks and intellectual property rights of SD belong to SD GROUP
All trademarks and brand names belong to their respective owners
2
Publication Release Date:Jul.2002
Revision 1.0
5 Page 
W83L518D
5 GENERAL-PURPOSE I/O PORTS (GPIO)
W83L518D supports one group of dedicated general-purpose I/O ports and a multi-functional GPIO group,
which share the same pines with the SD interface sockets. There are cases when only one socket is
needed in a system and pins for the other unused socket are wasted. To provide the most cost-effective
solution, W83L518D could be configured to transform these pins into general-purpose I/O ports.
The first group (GP10 ~ 17) is configured through the configuration registers CRF0 ~ CRF2 in logical
device 2 and the other group (GP20 ~27) through CRF3 ~ F5. Users can configure each individual port
to be an input or output port by programming respective bit in direction register (CRF0/CRF3: 0= output,
1 = input). Invert port value by setting inversion register (CRF2/CRF5: 0 = non-inverse, 1 = inverse). Port
value is read/written through data register (CRF1/CRF4). Table 5.1 and 5.2 illustrate GPIO's assignment.
To further facilitate system design, W83L518D allows direct accesses to data register and direction
register through I/O ports, whose base address is programmable at CR 60, 61 in logical device 2.
Detailed configuration is described in logical device 2 of section 6: CONFIGURATION REGISTER.
GP10 (pin 14) also functions as a power-on setting pin whose value is latched on the rising edge of
RESET# (pin 4) to select configuation port addresses. Therefore, GP10 is a push-pull I/O port unlike the
other GPIO ports, which are open-drained I/Os to support this power-on setting feature.
GP11 (pin 13) could function as a card detection input if selected by SDI to support some MMC cards,
which don't offer card detection feature through DATA3 pin.
Table 5.1
DIRECTION
BIT
0 = OUTPUT
1 = INPUT
0
0
1
1
INVERSION BIT
0 = NON
INVERSE
1 = INVERSE
0
1
0
1
I/O OPERATION
Basic non-inverting output
Basic inverting output
Basic non-inverting input
Basic inverting input
The trademarks and intellectual property rights of Memory Stick belong to SONY Corporation
The trademarks and intellectual property rights of SD belong to SD GROUP
All trademarks and brand names belong to their respective owners
8
Publication Release Date:Jul.2002
Revision 1.0
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet W83L518D.PDF ] | |
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