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PDF W83629D Data sheet ( Hoja de datos )

Número de pieza W83629D
Descripción PCI TO ISA BRIDGE SET
Fabricantes Winbond 
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PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
GENERAL DESCRIPTION
W83628F is a PCI-to-ISA bus conversion IC. W83629D is a condensed centralizer
IC for IRQ and DMA control. W83628F and W83629D together form a complete set
for the PCI-to-ISA bridge.
For the new generation Intel chipset Camino and Whitney, featuring LPC bus, there
is no support for ISA bus and slots. However the demand of ISA devices still exist.
For such case, W83628F plus W83629D are the best companion solution for the
non-ISA chipset. Also the packages of W83628F (128-QFP) and W83629D (48-
LQFP) had been chosen to be the most economic solution for save the M/B board
layout size and cost.
For the new generation chipset featuring LPC interface and support no ISA bus,
W83627HF/F (Winbond LPC I/O) together with the set of W83628F and W83629D
is the complete solution.
FEATURES
PCI to ISA Bridge
Full ISA Bus Support including ISA Masters
5V ISA and 3.3V PCI interfaces
PC/PCI DMA protocol for Software Transparent
IRQ Serializer for ISA Parallel IRQ transfer to Serial IRQ
Supports 3 fully ISA Compatible Slots without Buffering
PCI Bus at 25MHz, 33MHz and up to 40MHz
Supports Programmable ISA Bus Divide the PCI Bus Clock into 3 or 4
All ISA Signals can be Isolate
Supports Configuration registers for programming performance
PACKAGE
128-pin PQFP for W83628F
48-pin LQFP for W83629D
Publication Release Date: Dec 1998
- 1 - Revision 0.32

1 page




W83629D pdf
PCI TO ISA BRIDGE SET
W83628F & W83629D
PIN CONFIGURATION FOR 629D
D DD
A AA
D
D C D CD C D A D
R K R KR K G R C R V
N Q 7 Q 6Q 5 N Q K Q C
C 7 # 6 #5 # D 3 3 2 C
NC
NC
NC
NOGO
ISAREQ#
ISAGNT#
GND
PCICLK
NC
SERIRQ
PCIRST#
3VCC
36
37
25 24
W83629D
48
1
13
12
DACK2#
DRQ1
DACK1#
DRQ0
DACK0#
TC
GND
HS2
HS1
HS0
VCC
IRQ15
GI I I I I V I I I I I
N R RR RR C R R R R R
D Q Q Q Q Q CD Q Q Q Q Q
3 45 67 9 1 1 1 1
012 4
PRELIMINARY
Publication Release Date: Jan 1999
- 5 - Revision 0.32

5 Page





W83629D arduino
PCI TO ISA BRIDGE SET
W83628F & W83629D
PRELIMINARY
1.2 W83629D PIN DESCRIPTION
1.2.1 Control Logic and Handshaking Signals
SYMBOL
HS[2:0]
NOGO
PIN
17-15
40
I/O
I/O12
INt
FUNCTION
Handshaking Signals. HS[2:0] connected to W83628F for PCI
to ISA SET handshaking signals.
NO GO. This signal indicates which master initiated the current
transaction and also indicates whether or not the current bus
cycle is targeted for the ISA bus. This signal is a point-to-point
connection between PCI HOST Bridge and W83628F.
PCICLK
PCIRST#
44 INt PCI Bus System Clock. PCICLK provides timing for all
transactions on the PCI bus. All other PCI signals are sampled
on the rising edge of PCICLK, and all timing parameters are
defined with respect to this edge.
47 INt PCI Reset. W83628F receives PCIRST# as a reset from the PCI
Bus.
1.2.2 PC/PCI Interface
SYMBOL
ISAREQ#
ISAGNT#
DRQ
[7:5,3:0]
DACK
[7:5,3:0]#
TC
PIN
41
42
35,33
31,28
26,23
21
34,32
30,27
24,22
20
19
I/O
OUT24t
INt
INt
OUT24t
OUT24t
FUNCTION
ISA Bus Request. This signal is a point-to-point signal between
W83629D and a PCI HOST arbiter . The W83629D asserts this
signal according to the PC/PCI protocol.
ISA Bus Grant. This signal is a point-to-point signal between
W83629D and a PCI HOST Bridge’s secondary bus
PCPCIGNT# signal. W83629D asserts this signal according to
the PC/PCI protocol.
DMA Request. The DREQ signal indicates that either a slave
DMA device is requesting DMA services, or an ISA bus master is
requesting use of the ISA bus.
DMA Acknowledge. The DACK# signal indicates that either a
DMA channel or an ISA bus master has been granted the ISA
bus.
Terminal Count. The W83628F asserts TC to DMA slaves as a
terminal count indicator.
- 11 -
Publication Release Date: Jan 1999
Revision 0.32

11 Page







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