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PDF W83194R-67A Data sheet ( Hoja de datos )
| Número de pieza | W83194R-67A | |
| Descripción | 100MHZ 3-DIMM CLOCK FOR VIA MVP4 | |
| Fabricantes | Winbond | |
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W83194R-67A
100MHZ 3-DIMM CLOCK FOR VIA MVP4
1.0 GENERAL DESCRIPTION
The W83194R-67A is a Clock Synthesizer which provides all clocks required for high-speed RISC or
CISC microprocessor such as Intel Pentium , AMD and Cyrix. W83194R-67A provides sixteen
CPU/PCI frequencies which are externally selectable with smooth transitions. W83194R-67AA also
provides 13 SDRAM clocks controlled by the none-delay buffer_in pin.
The W83194R-67A accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
Spread spectrum built in at ¡Ó0.5% or ¡Ó0.25% to reduce EMI. Programmable stopping individual
clock outputs and frequency selection through I2C interface. The device meets the Pentium power-up
stabilization, which requires CPU and PCI clocks be stable within 2 ms after power-up.
High drive six PCI and thirteen SDRAM CLOCK outputs typically provide greater than 1 V /ns slew
rate into 30 pF loads. Two CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20
pF loads as maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48
MHz provide better than 0.5V /ns slew rate.
2.0 PRODUCT FEATURES
• Supports Pentium™ , AMD, Cyrix CPU with I2C.
• 4 CPU clocks (one free-running CPU clock)
• 13 SDRAM clocks for 3 DIMs
• 6 PCI synchronous clocks
• Optional single or mixed supply:
(Vddq1=Vddq2 = Vddq3 = Vddq4 = VddL1 =VddL2= 3.3V) or (Vddq1= Vddq2 = Vddq3=Vddq4 =
3.3V, VddL1 = VdqL2 = 2.5V)
• < 250ps skew among CPU and SDRAM clocks
• < 4ns propagation delay SDRAM from buffer input
• Skew from CPU(earlier) to PCI clock -1 to 4ns, center 2.6ns.
• Smooth frequency switch with selections from 60 MHz to 124 MHz CPU
• I2C 2-Wire serial interface and I2C read back
• ¡Ó0.25% or ¡Ó0.5% spread spectrum function to reduce EMI
• Programmable registers to enable/stop each output and select modes
(mode as Tri-state or Normal )
• 2ms power up clock stable time
• MODE pin for power Management
• One 48 MHz for USB & one 24 MHz for super I/O
• 48-pin SSOP package
Publication Release Date: Feb. 1999
- 1 - Revision 0.30
1 page  
W83194R-67A
6.0 FREQUENCY SELECTION
FS3 FS2 FS1 FS0 CPU,SDRAM(MHz) PCI(MHz)
11 1
11 1
11 0
11 0
10 1
10 1
10 0
10 0
1 60
0 66.8
1 70
0 90
1 80
0 83.3
1 95.25
0 100.2
30(CPU/2)
33.4(CPU/2)
35(CPU/2)
30(CPU/3)
26.67(CPU/3)
27.77(CPU/3)
31.75(CPU/3)
33.3(CPU/3)
01 1
01 1
01 0
01 0
00 1
00 1
00 0
00 0
1 75
0 80
1 83.3
0 105
1 110
0 115
1 120
0 124
37.5(CPU/2)
40(CPU/2)
41.65(CPU/2)
35(CPU/3)
36.67(CPU/3)
38.33(CPU/3)
40(CPU/3)
41.33(CPU/3)
PRELIMINARY
REF,IOAPIC (MHz)
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
7.0 MODE PIN -POWER MANAGEMENT INPUT CONTROL
MODE, Pin7 (Latched Input)
0
1
PIN 2
PCI_STOP# (Input)
REF0 (Output)
Publication Release Date: Feb. 1999
- 5 - Revision 0.30
5 Page 
W83194R-67A
PRELIMINARY
9.0 SPECIFICATIONS
9.1 ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed in this table may cause permanent damage to the device.
Precautions should be taken to avoid application of any voltage higher than the maximum rated
voltages to this circuit. Maximum conditions for extended periods may affect reliability. Unused
inputs must always be tied to an appropriate logic voltage level (Ground or Vdd).
Symbol
Vdd , VIN
TSTG
TB
TA
Parameter
Voltage on any pin with respect to GND
Storage Temperature
Ambient Temperature
Operating Temperature
Rating
- 0.5 V to + 7.0 V
- 65°C to + 150°C
- 55°C to + 125°C
0°C to + 70°C
9.2 AC CHARACTERISTICS
Vddq1=Vddq2 = Vddq3 = Vddq4 =3.3V , VddL1 =VddL2= 2.5V , TA = 0°C to +70°C
Parameter
Symbol Min Typ Max Units
Test Conditions
Output Duty Cycle
45 50
55
% Measured at 1.5V
CPU/SDRAM to PCI Offset tOFF
1
4 ns 15 pF Load Measured at 1.5V
Skew (CPU-CPU), (PCI-
PCI), (SDRAM-SDRAM)
CPU/SDRAM
Cycle to Cycle Jitter
tSKEW
tCCJ
250
¡Ó250
ps 15 pF Load Measured at 1.5V
ps
CPU/SDRAM
Absolute Jitter
tJA
500 ps
Jitter Spectrum 20 dB
BWJ
500 KHz
Bandwidth from Center
Output Rise (0.4V ~ 2.0V)
& Fall (2.0V ~0.4V) Time
tTLH 0.4
tTHL
1.6 ns 15 pF Load on CPU and PCI
outputs
Overshoot/Undershoot
Beyond Power Rails
Vover
1.5 V 22 Ω at source of 8 inch PCB
run to 15 pF load
Ring Back Exclusion
VRBE
2.1 V Ring Back must not enter this
range.
- 11 -
Publication Release Date: Feb. 1999
Revision 0.30
11 Page | ||
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| PDF Descargar | [ Datasheet W83194R-67A.PDF ] | |
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