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PDF W78LE54 Data sheet ( Hoja de datos )

Número de pieza W78LE54
Descripción 8-BIT MTP MICROCONTROLLER
Fabricantes Winbond 
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Preliminary W78LE54
8-BIT MTP MICROCONTROLLER
GENERAL DESCRIPTION
The W78LE54 is an 8-bit microcontroller which can accommodate a wide supply voltage range with
low power consumption. The instruction set for the W78LE54 is fully compatible with the standard
8051. The W78LE54 contains an 16K bytes MTP ROM (Multiple-Time Programmable ROM); a 256
bytes RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit I/O port P4; three
16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported
by eight sources two-level interrupt capability. To facilitate programming and verification, the MTP-
ROM inside the W78LE54 allows the program memory to be programmed and read electronically.
Once the code is confirmed, the user can protect the code for security.
The W78LE54 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
Fully static design 8-bit CMOS microcontroller
Wide supply voltage of 2.4V to 5.5V
256 bytes of on-chip scratchpad RAM
16 KB electrically erasable/programmable MTP-ROM
64 KB program memory address space
64 KB data memory address space
Four 8-bit bi-directional ports
One extra 4-bit bit-addressable I/O port, additional INT2 / INT3
(available on 44-pin PLCC/QFP package)
Three 16-bit timer/counters
One full duplex serial port(UART)
Watchdog Timer
Eight sources, two-level interrupt capability
EMI reduction mode
Built-in power management
Code protection mechanism
Packages:
DIP 40: W78LE54-24
PLCC 44: W78LE54P-24
PQFP 44: W78LE54F-24
Publication Release Date: February 1999
- 1 - Revision A1

1 page




W78LE54 pdf
Preliminary W78LE54
reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
1. INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3 EX3 IE3
IT3 PX2 EX2 IE2
IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Eight-source interrupt informations:
INTERRUPT
SOURCE
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
Timer/Counter 2
External Interrupt 2
External Interrupt 3
VECTOR
ADDRESS
03H
0BH
13H
1BH
23H
2BH
33H
3BH
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
0 (highest)
1
2
3
4
5
6
7 (lowest)
ENABLE
REQUIRED
SETTINGS
IE.0
IE.1
IE.2
IE.3
IE.4
IE.5
XICON.2
XICON.6
INTERRUPT
TYPE
EDGE/LEVEL
TCON.0
-
TCON.2
-
-
-
XICON.0
XICON.3
2. PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
Publication Release Date: February 1999
- 5 - Revision A1

5 Page





W78LE54 arduino
Preliminary W78LE54
D7 D6 D5 D4 D3 D2 D1 D0
11011010
Company ID (#DAH)
16KB MTP ROM
0000h
01100001
Device ID (#61H)
Program Memory
B7 Reserved B2 B1 B0
Security Bits
Reserved
B0 : Lock bit, logic 0 : active
B1 : MOVC inhibit,
logic 0 : the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1 : no restriction.
B2 : Encryption
logic 0 : the encryption logic enable
logic 1 : the encryption logic disable
Security Register
B7 : Osillator Control
logic 0 : 1/2 gain
logic 1 : Full gain
Default 1 for all security bits.
Reserved bits must be kept in logic 1.
Special Setting Registers
3FFFh
0FFFFh
Lock bit
This bit is used to protect the customer's program code in the W78LE54. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
MTP ROM data and Special Setting Registers can not be accessed again.
MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set
to logic 0, a MOVC instruction in external program memory space will be able to access code only in
the external memory, not in the internal memory. A MOVC instruction in internal program memory
space will always be able to access the ROM data in both internal and external memory. If this bit is
logic 1, there are no restrictions on the MOVC instruction.
Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
+5V +5V
A0 to A7
VIL
VIL
VIL
VIL
VIL
VIH
P1
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
X'tal1
X'tal2
Vss
VDD
P0
EA/Vpp
ALE
RST
PSEN
P2
PGM DATA
VCP
VIL
VIH
VIH
A8 to A15
A0 to A7
VIL
VIL
VIL
VIL
VIH
VIL
P1
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
X'tal1
X'tal2
Vss
VDD
P0
EA/Vpp
ALE
RST
PSEN
P2
PGM DATA
VCP
VIL
VIH
VIH
A8 to A15
Programming Configuration
Programming Verification
- 11 -
Publication Release Date: February 1999
Revision A1

11 Page







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