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PDF W6630CR Data sheet ( Hoja de datos )
| Número de pieza | W6630CR | |
| Descripción | STEREO AUDIO DAC | |
| Fabricantes | Winbond | |
| Logotipo |  |
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Preliminary W6630CR
STEREO AUDIO DAC
1. GENERAL DESCRIPTION
The Winbond W6630 is a stereo audio DAC chip incorporating 8X digital interpolatioin filters, 64X
multi-level oversampling delta-sigma modulators, analog low-pass filter and output amplifiers. The
operation voltage for this chip can be from 2.7 volt to 5.25 volt. Moreover, the 16 or 18 Bit linear input
data for DAC consists of two formats, normal format and I2S format. In addition, the device includes
two control modes. One is hardware mode which can control mute and digital de-emphasis. The other
one is software mode, where 4 x 9 bits internal control registers can be controlled by the serial setup
port (SSP). Many functions such as 256 step attenuation, DAC mute, digital de-emphasis and format
conversions can be setup through these registers.
Because the device can reach into the high performance and low-cost design , the main application
for this device is used as some consumers system such as the VCD system, CD player system, and
MPEG audio system .
2. FEATURES
• Power Supply from +2.7 to +5.25 Volt, typically +5 Volt, for Analog and Digital Power
• Sampling Clock Rate: 32 K, 44.1 K, and 48 KHz
• Master Clock Rate: 384 or 256 times of Sampling Clock Rate
• Stereo 16 or 18 Bits Linear PCM Data Input
• Two Types Linear PCM Data Input Format: Normal and I2S Format
• Delta-Sigma DAC built-in digital De-emphasis filter, 8X Interpolator, 64X Oversampling Multi-Bit
Modulator
• Stereo DAC Output built-in Analog Low Pass Filter and Ouput Amplifier with 5K Ω Load
• High Performance Audio Output: 100 dB SNR, 96 dB Dynamic Range and -90 dB THD+N
• Two Control Function Modes: Hardware Mode and Software Mode Selected by Mode Pin
• Software Mode Controlled by 4x9 bits Registers via Serial Setup Port (SSP)
• Main Control Functions: De-emphasis, Mute, 256 Step Attenuation, Channel Output Combination,
• Input Format Select such as 16 or 18 Bit, I2S or Normal.
• Packaged in 20 pin SSOP
Publication Release Date: December 1998
- 1 - Revision A1
1 page  
Preliminary W6630CR
6. FUNCTIONAL DESCRIPTIONS
Figure 5 illustrates the functional blocks of the Winbond's stereo 16 or 18 bit audio DAC .
6.1. Power Supply Management System
6.1.1. Power Supply for All Analog Signals Processing
All analog circuits are supplied with AVDD from +2.7 volt to 5.25 volt, typically +5 volt. In addition, the
AVDD pin should be decoupled to AGND pin with a 0.1 µF capacitor.
6.1.2. Power Supply for All Digital Signals Processing
All digital circuits are supplied with DVDD from +2.7 volt to 5.25 volt, typically +5 volt. In addition, the
DVDD pin should be decoupled to DGND pin with a 0.1 uF capacitor.
6.1.3. Analog Signal Ground Voltage Control System
The analog ground output for the left channel refers to VAGL pin, typically half of AVDD. Moreover
the analog ground output for the right channel refers to VAGR pin, typically half of AVDD. These two
pin should be connected to AGND pin with a 10 µF capacitor.
6.2. Delta-Sigma DAC-Filter
This device has built in stereo linear 16 or 18-bit D/A converter (DAC)- filter based on the delta-sigma
technology. The linear input data from DINLR pin including the left and right channel are fed into the
8-times interpolation filter with -40 dB stop band attenuation and +- 0.15 dB ripple in the pass band,
shown in Figure 6-1. Then the filtered data is quantized by 64-time oversampling multi-bit delta-sigma
modulator whether the sampling rate is 256-times or 384-times sampling clock rate. The modulator is
a 3rd-order noise shaper with multi-level amplitude quantizer. The structure is shown in Figure 6-2.
And the quantization noise performance of the multi-level modulator is shown in Figure 6-3.The the
quantized values are passed into the analog DAC for the left and right channel separtedly. Finally, the
data are sented the analog low pass filter and output amplifer to generate the analog signal output at
the VOL pin for the left channel , and at the VOR pin for the right channel.
6.3. Data Conversion
This block is the digital data conversion circuit. It consists of serial data port (SDP), serial setup port
(SSP) with 4 x 9 registers, and mode function control block.
6.3.1. Serial Data Port (SDP)
This SDP block will convert the data input from DINLR pin into parallel data, separated into the left
and right channel, depended on I2S or normal data input format and 384-times or 256-times sampling
clock rate. The timing diagram are shown in Figure 6-5 and 6-6. In the I2S format, the data is
compatible with Philips serial data protocol, the MSB bit is shifted into SDP block at the rising edge of
second BCLK, and the following data bit are shifted into the SDP port at the following rising edge of
sequence BCLK. Moreover when the FSLR is in low, the input data is corresponding to the left
channel; and when the FSR is logic-1, the input data is corresponding to the right channel. For the
normal format, the LSB bit is justified to the transition of FSLR pin, and the MSB bit is the first bit
presented on the input data sequence. The data are latched into the SDP port same as the I2S format
at the rising edge of BCLK. But the left or right channel input location is reversed with I2S format. In
other word, the logic-one in the FSLR is the left channel data; and the logic-zero in the FSLR pin is
the right channel data for the Normal data format. The FSLR pin is the sampling clcok rate. For this
device, it should be 32K, 44.1K or 48 KHz input. All input data, whether is 16 or 18 bit, are 2's
complement.
Publication Release Date: December 1998
- 5 - Revision A1
5 Page 
Preliminary W6630CR
Continued
FUNCTION
De-emphasis
Control
L/R Attenuation
Control
Mute Control
Zero Detection
Channel Ouput
Type Control
S/W SELECTION S/W DEFAULT H/W SELECTION
32K, 44.1K, 48K,
and Off
(CR2[2:1])
Off
32K, 44.1K, 48K,
and Off
(Pin17, Pin 16)
8 Bits attenuation
for L/R Channel
(L:CR0[7:0])
(R:CR1[7:0])
0 dB
Not Support
Yes
(CR2[0])
Off
Yes
Yes
(CR2[4])
Off Not Support
Yes
(CR3[7:4])
L_chan = L
R_chan = R
Not Support
Table 7-1. The Comparison between the Software Mode and Hardware Mode
H/W DEFAULT
Off
0 dB
Off
Off
L_chan = L
R_chan = R
PIN 17(DE1)
0
0
1
1
PIN 16(DE0)
FUNCTION
0 Disable the digital de-emphasis filter
1 Enable the digital de-emphasis filter at 48 KHz
0 Enable the digital de-emphasis filter at 44.1 KHz
1 Enable the digital de-emphasis filter at 32 KHz
Table 7-2 Digital De-emphasis Filter Configuration in Hardware Mode
7.2. Control Registers in Software Mode
There are 4x9-bit registers for controlling the chip in the software mode. These registers are labeled
CR0 to CR3. The descriptions are as follows. Note that "setting" is corresponding to logic "1" and
"clearing" is corresponding to logic "0". In addition, the res bit indicates the reserved bit and must be
logic-0. Because the first 5 bits are res bit and the data must be logic-0; the next 2 bits are address
bits, A1 and A0 to select control register shown in Table 7-3; the final 9 bits are the actual configured
data input bits. The following control register only show how to control the configured data bits. In
other word, the control register only show Bit[9:0]. The detail timing is shown in the Figure 6-3.
A1 A0
CONTROL REGISTER SELECTION
0 0 Select Control register 0 (CR0)
0 1 Select Control register 1 (CR1)
1 0 Select Control register 2 (CR2)
1 1 Select Control register 3 (CR3)
Table 7-3 Control Register Selection
- 11 -
Publication Release Date: December 1998
Revision A1
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet W6630CR.PDF ] | |
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