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PDF PCF8591 Data sheet ( Hoja de datos )

Número de pieza PCF8591
Descripción 8-bit A/D and D/A converter
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! PCF8591 Hoja de datos, Descripción, Manual

PCF8591
8-bit A/D and D/A converter
Rev. 7 — 27 June 2013
Product data sheet
1. General description
The PCF8591 is a single-chip, single-supply low-power 8-bit CMOS data acquisition
device with four analog inputs, one analog output and a serial I2C-bus interface. Three
address pins A0, A1 and A2 are used for programming the hardware address, allowing
the use of up to eight devices connected to the I2C-bus without additional hardware.
Address, control and data to and from the device are transferred serially via the two-line
bidirectional I2C-bus.
The functions of the device include analog input multiplexing, on-chip track and hold
function, 8-bit analog-to-digital conversion and an 8-bit digital-to-analog conversion. The
maximum conversion rate is given by the maximum speed of the I2C-bus.
2. Features and benefits
Single power supply
Operating supply voltage 2.5 V to 6.0 V
Low standby current
Serial input and output via I2C-bus
I2C address selection by 3 hardware address pins
Max sampling rate given by I2C-bus speed
4 analog inputs configurable as single ended or differential inputs
Auto-incremented channel selection
Analog voltage range from VSS to VDD
On-chip track and hold circuit
8-bit successive approximation A/D conversion
Multiplying DAC with one analog output.
3. Applications
Supply monitoring
Reference setting
Analog control loops

1 page




PCF8591 pdf
NXP Semiconductors
PCF8591
8-bit A/D and D/A converter
8. Functional description
8.1 Addressing
Each PCF8591 device in an I2C-bus system is activated by sending a valid address to the
device. The address consists of a fixed part and a programmable part. The programmable
part must be set according to the address pins A0, A1 and A2. The address is always sent
as the first byte after the start condition in the I2C-bus protocol. The last bit of the address
byte is the read/write-bit which sets the direction of the following data transfer (see Table 5
on page 13, Figure 15 on page 13 and Figure 16 on page 13).
8.2 Control byte
The second byte sent to a PCF8591 device is stored in its control register and is required
to control the device function. The upper nibble of the control register is used for enabling
the analog output, and for programming the analog inputs as single-ended or differential
inputs. The lower nibble selects one of the analog input channels defined by the upper
nibble (see Figure 4). If the auto-increment flag is set, the channel number is incremented
automatically after each A/D conversion.
If the auto-increment mode is desired in applications where the internal oscillator is used,
the analog output enable flag must be set in the control byte (bit 6). This allows the
internal oscillator to run continuously, by this means preventing conversion errors
resulting from oscillator start-up delay. The analog output enable flag can be reset at other
times to reduce quiescent power consumption.
The selection of a non-existing input channel results in the highest available channel
number being allocated. Therefore, if the auto-increment flag is set, the next selected
channel is always channel 0. The most significant bits of both nibbles are reserved for
possible future functions and must be set to logic 0. After a Power-On Reset (POR)
condition, all bits of the control register are reset to logic 0. The D/A converter and the
oscillator are disabled for power saving. The analog output is switched to a
high-impedance state.
PCF8591
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 27 June 2013
© NXP B.V. 2013. All rights reserved.
5 of 31

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PCF8591 arduino
NXP Semiconductors
PCF8591
8-bit A/D and D/A converter
9. Characteristics of the I2C bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only
when the bus is not busy.
9.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse, as changes in the data line at this time
are interpreted as a control signal (see Figure 11).
SDA
SCL
Fig 11. Bit transfer
data line
stable;
data valid
change
of data
allowed
mbc 621
9.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 12).
SDA
SDA
SCL
S
START condition
Fig 12. Definition of START and STOP conditions
P
STOP condition
SCL
mbc 622
9.3 System configuration
A device generating a message is a transmitter; a device receiving a message is a
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves (see Figure 13).
PCF8591
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 27 June 2013
© NXP B.V. 2013. All rights reserved.
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