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PDF PCF8584P Data sheet ( Hoja de datos )

Número de pieza PCF8584P
Descripción I2C-bus controller
Fabricantes NXP Semiconductors 
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No Preview Available ! PCF8584P Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
PCF8584
I2C-bus controller
Product specification
Supersedes data of 1997 Mar 19
File under Integrated Circuits, IC12
1997 Oct 21

1 page




PCF8584P pdf
Philips Semiconductors
I2C-bus controller
Product specification
PCF8584
5 PINNING
SYMBOL
CLK
SDA or
SDA OUT
SCL or SCL IN
IACK or
SDA IN
PIN
1
2
3
4
INT or
SCL OUT
5
A0 6
DB0
DB1
DB2
VSS
DB3
DB4
DB5
DB6
DB7
RD (DTACK)
CS
WR (R/W)
RESET/
STROBE
VDD
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O
I
I/O
I/O
I
O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/(O)
I
I
I/O
DESCRIPTION
clock input from microcontroller clock generator (internal pull-up)
I2C-bus serial data input/output (open-drain). Serial data output in long-distance
mode.
I2C-serial clock input/output (open-drain). Serial clock input in long-distance mode.
Interrupt acknowledge input (internal pull-up); when this signal is asserted the
interrupt vector in register S3 will be available at the bus Port if the ENI flag is set.
Serial data input in long-distance mode.
Interrupt output (open-drain); this signal is enabled by the ENI flag in register S1.
It is asserted when the PIN flag is reset. (PIN is reset after 1 byte is transmitted or
received over the I2C-bus). Serial clock output in long-distance mode.
Register select input (internal pull-up); this input selects between the control/status
register and the other registers. Logic 1 selects register S1, logic 0 selects one of
the other registers depending on bits loaded in ESO, ES1 and ES2 of register S1.
bidirectional 8-bit bus Port 0
bidirectional 8-bit bus Port 1
bidirectional 8-bit bus Port 2
ground
bidirectional 8-bit bus Port 3
bidirectional 8-bit bus Port 4
bidirectional 8-bit bus Port 5
bidirectional 8-bit bus Port 6
bidirectional 8-bit bus Port 7
RD is the read control input for MAB8049, MAB8051 or Z80-types. DTACK is the
data transfer control output for 68000-types (open-drain).
chip select input (internal pull-up)
WR is the write control input for MAB8048, MAB8051, or Z80-types
(internal pull-up). R/W control input for 68000-types.
Reset input (open-drain); this input forces the I2C-bus controller into a predefined
state; all flags are reset, except PIN, which is set. Also functions as strobe output.
supply voltage
1997 Oct 21
5

5 Page





PCF8584P arduino
Philips Semiconductors
I2C-bus controller
Product specification
PCF8584
6.8.1.5 STA and STO
These bits control the generation of the I2C-bus START condition and transmission of slave address and R/W bit,
generation of repeated START condition, and generation of the STOP condition (see Table 7).
Table 6 Register access control; ESO = 1 (serial interface on) and ES1 = 1; long-distance (4-wire) mode; note 1
INTERNAL REGISTER ADDRESSING: LONG-DISTANCE (4-WIRE) MODE
A0 ES1 ES2 IACK
FUNCTION
1 1 X 1 W S1: control
1 1 X X R S1; status
0 1 X X R/W S0; (data)
Note
1. Trying to read from or write to registers other than S0 and S1 (setting ESO = 0) brings the PCF8584 out of the
long-distance mode.
Table 7 Instruction table for serial bus control
STA
STO
PRESENT
MODE
FUNCTION
OPERATION
1
0
SLV/REC
START
transmit START + address, remain
MST/TRM if R/W = 0;
go to MST/REC if R/W = 1
1
0
MST/TRM
REPEAT same as for SLV/REC
START
0
1
MST/REC;
STOP READ; transmit STOP go to SLV/REC mode; note 1
MST/TRM
STOP WRITE
1
1
MST
DATA
send STOP, START and address after last
CHAINING master frame without STOP sent; note 2
0
0
ANY
NOP
no operation; note 3
Notes
1. In master receiver mode, the last byte must be terminated with ACK bit HIGH (‘negative acknowledge’).
2. If both STA and STO are set HIGH simultaneously in master mode, a STOP condition followed by a START
condition + address will be generated. This allows ‘chaining’ of transmissions without relinquishing bus control.
3. All other STA and STO mode combinations not mentioned in Table 7 are NOPs.
6.8.1.6 ACK
This bit must be set normally to a logic 1. This causes the I2C-bus controller to send an acknowledge automatically after
each byte (this occurs during the 9th clock pulse). The bit must be reset (to logic 0) when the I2C-bus controller is
operating in master/receiver mode and requires no further data to be sent from the slave transmitter. This causes a
negative acknowledge on the I2C-bus, which halts further transmission from the slave device.
6.8.2 REGISTER S1 STATUS SECTION
The read-only section of S1 enables access to I2C-bus status information; see Table 4.
1997 Oct 21
11

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