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PDF W149 Data sheet ( Hoja de datos )

Número de pieza W149
Descripción 440BX AGPset Spread Spectrum Frequency Synthesizer
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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W149
440BX AGPset Spread Spectrum Frequency Synthesizer
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Single chip system frequency synthesizer for Intel®
440BX AGPset
• Two copies of CPU output
• Six copies of PCI output
• One 48-MHz output for USB
• One 24-MHz output for SIO
• Two buffered reference outputs
• One IOAPIC output
• Thirteen SDRAM outputs provide support for 3 DIMMs
• Spread Spectrum feature always enabled
• I2C™ interface for programming
• Power management control inputs
• Smooth CPU frequency switching from 66.8–124 MHz
Key Specifications
CPU Cycle-to-Cycle Jitter: ......................................... 250 ps
CPU to CPU Output Skew: ........................................ 175 ps
PCI to PCI Output Skew: ............................................ 500 ps
VDDQ3: ..................................................................... 3.3V±5%
VDDQ2: ..................................................................... 2.5V±5%
SDRAMIN to SDRAM0:12 Delay:.......................... 3.7 ns typ.
Table 1. Mode Input Table[1]
Mode
Pin 2
0 PCI_STOP#
1 REF0
Table 2. Pin Selectable Frequency
Input Address CPU0:1
FS2 FS1 FS0 (MHz)
PCI_F, 1:5
(MHz)
111
100 33.3 (CPU/3)
110
(Reserved)
101
100 33.3 (CPU/3)
100
103 34.3 (CPU/3)
011
66.8 33.4 (CPU/2)
010
83.3 41.7 (CPU/2)
001
66.8 33.4 (CPU/2)
000
124 41.3 (CPU/3)
Spread
%
–0.5
±0.5
–0.5
–0.5
–0.5
±0.5
–0.5
Logic Block Diagram
X1 XTAL
X2 OSC
PLL Ref Freq
I/O Pin
Control
PLL 1
÷2/÷3
Stop
Clock
Control
VDDQ3
REF0/(PCI_STOP#)
REF1/FS2
VDDQ2
IOAPIC
VDDQ2
CPU0
CPU1
VDDQ3
PCI_F/MODE
PCI1
PCI2
PCI3
PCI4
Pin Configuration[2]
VDDQ3
REF0/(PCI_STOP#)
GND
X1
X2
VDDQ3
PCI_F/MODE
PCI1
GND
PCI2
PCI3
PCI4
PCI5
VDDQ3
SDRAMIN
GND
SDRAM11
SDRAM10
VDDQ3
SDRAM9
SDRAM8
GND
{I2C SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDQ2
47 IOAPIC
46 REF1/FS2*
45 GND
44 CPU0
43 CPU1
42 VDDQ2
41 OE
40 SDRAM12
39 GND
38 SDRAM0
37 SDRAM1
36 VDDQ3
35 SDRAM2
34 SDRAM3
33 GND
32 SDRAM4
31 SDRAM5
30 VDDQ3
29 SDRAM6
28 SDRAM7
27 VDDQ3
26 48MHz/FS0*
25 24MHz/FS1*
SDATA
SCLK
I2C
Logic
PCI5
PLL2
VDDQ3
48MHz/FS0
÷2
SDRAMIN
24MHz/FS1
VDDQ3
SDRAM0:12
13
Intel is a registered trademark of Intel Corporation. I2C is a trademark of Philips Corporation.
Notes:
1. Mode input latched at power-up.
2. Internal pull up resistors(*) should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
July 31, 2000 rev. *A

1 page




W149 pdf
W149
Serial Data Interface
The W149 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions. Upon power-up, the W149 initializes with
default register settings, therefore the use of this serial data
interface is optional. The serial interface is write-only (to the
clock chip) and is the dedicated function of device pins SDATA
and SCLOCK. In motherboard applications, SDATA and
SCLOCK are typically driven by two logic outputs of the
chipset. Clock device register changes are normally made
upon system initialization, if any are required. The interface
can also be used during system operation for power manage-
ment functions. Table 3 summarizes the control functions of
the serial data interface.
Operation
Data is written to the W149 in eleven bytes of eight bits each.
Bytes are written in the order shown in Table 4.
Table 3. Serial Data Interface Control Functions Summary
Control Function
Clock Output Disable
CPU Clock Frequency
Selection
Output Three-state
(Reserved)
Description
Any individual clock output(s) can be disabled.
Disabled outputs are actively held LOW.
Provides CPU/PCI frequency selections through
software. Frequency is changed in a smooth and
controlled fashion.
Puts clock output into a high-impedance state.
Reserved function for future device revision or
production device testing.
Common Application
Unused outputs are disabled to reduce EMI
and system power. Examples are clock
outputs to unused PCI slots.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change
under normal system operation.
Production PCB testing.
No user application. Register bit must be
written as 0.
Table 4. Byte Writing Sequence
Byte
Sequence
1
Byte Name
Slave Address
Bit Sequence
11010010
2 Command Code Dont Care
3 Byte Count
Dont Care
4 Data Byte 0
5 Data Byte 1
6 Data Byte 2
7 Data Byte 3
8 Data Byte 4
9 Data Byte 5
10 Data Byte 6
11 Data Byte 7
Refer to Table 5
Byte Description
Commands the W149 to accept the bits in Data Bytes 06 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W149 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
Unused by the W149, therefore bit values are ignored (Dont Care).
This byte must be included in the data write sequence to maintain prop-
er byte allocation. The Command Code Byte is part of the standard
serial communication protocol and may be used when writing to anoth-
er addressed slave receiver on the serial data bus.
Unused by the W149, therefore bit values are ignored (Dont Care).
This byte must be included in the data write sequence to maintain prop-
er byte allocation. The Byte Count Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
The data bits in Data Bytes 07 set internal W149 registers that control
device operation. The data bits are only accepted when the Address
Byte bit sequence is 11010010, as noted above. For description of bit
control functions, refer to Table 5, Data Byte Serial Configuration Map.
5

5 Page





W149 arduino
W149
SDRAM Clock Outputs, SDRAM, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)
CPU = 66.6 MHz
Parameter
Description
Test Condition/Comments Min. Typ. Max.
tP Period
tH High Time
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V,
at min. sdge rate (1.5 V/ns)
30
5.6
tL Low Time
Duration of clock cycle below 0.4V, 5.3
at min. sdge rate (1.5 V/ns)
tR
Output Rise Edge Measured from 0.4V to 2.4V
1.5
Rate
4
tF
Output Fall Edge
Measured from 2.4V to 0.4V
1.5
Rate
4
tPLH
Prop Delay LH
Input edge rate faster than 1 V/ns 1
tPHL
Prop Delay HL
Input edge rate faster than 1 V/ns 1
tD Duty Cycle
Measured on rising and falling
edge at 1.5V, at min. sdge rate
(1.5 V/ns)
45
5
5
55
tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.5V.
Maximum difference of cycle time
between two adjacent cycles.
250
tSK Output Skew Measured on rising edge at 1.5V
tO CPU to PCI Clock Covers all CPU/PCI outputs. Mea- 1.5
Skew
sured on rising edge at 1.5V. CPU
leads PCI output.
250
4
fST Frequency
Assumes full supply voltage
Stabilization from
reached within 1 ms from
Power-up (cold start) power-up. Short cycles exist prior
to frequency stabilization.
3
Zo AC Output
Impedance
Average value during switching
transition. Used for determining
series termination value.
30
CPU = 100 MHz
Min. Typ. Max. Unit
30 ns
3.3 ns
3.1 ns
1.5 4 V/ns
1.5 4 V/ns
1 5 ns
1 5 ns
45 55 %
250 ps
250 ps
1.5 4 ns
3 ms
30
11

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