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PDF PCF8577C Data sheet ( Hoja de datos )
| Número de pieza | PCF8577C | |
| Descripción | LCD direct/duplex driver | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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PCF8577C
LCD direct/duplex driver with I²C-bus interface
Rev. 5 — 10 October 2014
Product data sheet
1. General description
The PCF8577C is an LCD driver which drives up to 32 segments directly, or 64 segments
in a duplex configuration.
The two-line I2C-bus interface substantially reduces wiring overheads in remote display
applications. I2C-bus traffic is minimized in multiple IC applications by automatic address
incrementing, hardware subaddressing and display memory switching (direct drive
mode).To allow partial VDD shutdown, the ESD protection system of the SCL and SDA
pins does not use a diode connected to VDD.
For a selection of NXP LCD segment drivers, see Table 13 on page 25.
2. Features and benefits
Direct/duplex drive modes with up to 32/64 LCD-segment drive capability per device
Operating supply voltage: 2.5 V to 6 V
Low power consumption
I2C-bus interface
Optimized pinning for single plane wiring
Single-pin built-in oscillator
Auto-incremented loading across device subaddress boundaries
Display memory switching in direct drive mode
May be used as I2C-bus output expander
System expansion up to 256 segments
Power-on reset blanks display
I2C-bus address: 0111 0100.
3. Ordering information
Table 1. Ordering information
Type number
Package
Name
PCF8577CT
VSO40
Description
plastic very small outline package; 40
leads
Version
SOT158-1
1 page  
NXP Semiconductors
PCF8577C
LCD direct/duplex driver with I²C-bus interface
7.3 User-accessible registers
There are nine user-accessible 1-byte registers. The first is a control register which is
used to control the loading of data into the segment byte registers and to select display
options. The other eight are segment byte registers, split into two banks of storage, which
store the segment data. The set of even-numbered segment byte registers is called
BANK A. Odd-numbered segment byte registers are called BANK B.
There is one slave address for the PCF8577C (see Table 7). All addressed devices load
the second byte into the control register and each device maintains an identical copy of
the control byte in the control register always (see I2C-bus protocol, Figure 10), i.e. all
addressed devices respond to control commands sent on the I2C-bus.
The control register is shown in more detail in Figure 3. The least-significant bits select
which device and which segment byte register is loaded next. This part of the register is
therefore called the Segment Byte Vector (SBV).
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Fig 3. PCF8577C register organization
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The upper three bits of the SBV (V5 to V3) are compared with the hardware subaddress
input signals A2, A1 and A0. If they are the same, then the device is enabled for loading, if
not the device ignores incoming data but remains active.
The three least-significant bits of the SBV (V2 to V0) address one of the segment byte
registers within the enabled chip for loading segment data.
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 33
5 Page 
NXP Semiconductors
PCF8577C
LCD direct/duplex driver with I²C-bus interface
8.3 I2C-bus protocol
The PCF8577C I2C-bus protocol is shown in Figure 10.
The PCF8577C is a slave receiver and has a fixed slave address (see Table 7). All
PCF8577Cs with the same slave address acknowledge the slave address in parallel.
The second byte is always the control byte and is loaded into the control register of each
PCF8577C connected to the I2C-bus. All addressed devices acknowledge the control
byte. Subsequent data bytes are loaded into the segment registers of the selected device.
Any number of data bytes may be loaded in one transfer and in an expanded system
rollover of the SBV from 111 111 to 000 000 is allowed. If a STOP (P) condition is given
after the control byte acknowledge, the segment data remains unchanged. This allows the
BANK bit to be toggled without changing the segment register contents. During loading of
segment data, only the selected PCF8577C gives an acknowledge. Loading is terminated
by generating a STOP (P) condition.
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Fig 10. I2C-bus protocol
DDD
9. Safety notes
CAUTION
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
CAUTION
Semiconductors are light sensitive. Exposure to light sources can cause the IC to
malfunction. The IC must be protected against light. The protection must be applied to all
sides of the IC.
PCF8577C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 10 October 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 33
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| PDF Descargar | [ Datasheet PCF8577C.PDF ] | |
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