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Número de pieza | W130 | |
Descripción | Spread Spectrum Desktop/Notebook System Clock | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de W130 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
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W130
Spread Spectrum Desktop/Notebook System Clock
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Six copies of CPU Clock
• Eight copies of PCI Clock (synchronous w/CPU clock)
• Two copies of 14.318-MHz IOAPIC Clock
• Two copies of 48-MHz USB Clock
• Three buffered copies of 14.318-MHz reference input
• Input is a 14.318-MHz XTAL or reference signal
• Selectable 100-MHz or 66-MHz CPU Clocks
• Power management control input pins
• Test mode and output three-state capability
Key Specifications
Supply Voltages: ....................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
CPU Clock Jitter: ........................................................ 200 ps
CPU0:5 Clock Skew: ...................................................175 ps
PCI_F, PCI1:7 Clock Skew: ......................................... 500 ps
CPU to PCI Clock Skew: .............. 1.5 to 4.0 ns (CPU Leads)
Logic inputs have 250-kΩ pull-up resistors except SEL100/66#.
Table 1. Pin Selectable Frequency
SEL
100/66# SEL1 SEL0 CPU PCI SPREAD#=0
0 0 0 HI-Z HI-Z Don’t Care
0 0 1 66.6 33.3 ±0.9% Center
0 1 0 66.6 33.3 –1% Down
0 1 1 66.6 33.3 –0.5% Down
1 0 0 X1/2 X1/6 Don’t Care
1 0 1 100 33.3 ±0.9% Center
1 1 0 100 33.3 –1% Down
1 1 1 100 33.3 –0.5% Down
Block Diagram
X1 XTAL
X2 OSC
PLL Ref Freq
CPU_STOP#
100/66#_SEL
SEL0
SEL1
SPREAD#
PCI_STOP#
Stop
Clock
Control
PLL 1
÷2/÷3
Stop
Clock
Control
PWR_DWN#
PPowerr
DDoowwnn
CCoonnttrrooll
PLL2
VDDQ3
REF0
REF1
REF2
VDDQ2
APIC0
APIC1
VDDQ2
CPU0
CPU1
CPU2
CPU3
CPU4
CPU5
VDDQ3
PCI_F
PCI1
PCI2
PCI3
VDDQ3
PCI4
PCI5
PCI6
PCI7
VDDQ3
48MHz
48MHz
Pin Configuration
REF0
REF1
GND
X1
X2
GND
PCI_F
PCI1
VDDQ3
PCI2
PCI3
GND
PCI4
PCI5
VDDQ3
PCI6
PCI7
GND
VDDQ3
GND
VDDQ3
48MHz
48MHz
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 VDDQ3
47 REF2
46 VDDQ2
45 APIC0
44 APIC1
43 VDDQ2
42 CPU0
41 CPU1
40 CPU2
39 CPU3
38 GND
37 VDDQ2
36 CPU4
35 CPU5
34 GND
33 VDDQ3
32 GND
31 PCI_STOP#
30 CPU_STOP#
29 PWRDWN#
28 SPREAD#
27 SEL0
26 SEL1
25 SEL100/66#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 27, 1999, rev. **
1 page PRELIMINARY
W130
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% (continued)
Parameter
Description
Test Condition
Min. Typ. Max.
Unit
Crystal Oscillator
VTH
CLOAD
CIN,X1
X1 Input Threshold Voltage[3]
Load Capacitance, as seen by External Crystal[4]
X1 Input Capacitance[5]
Pin Capacitance/Inductance
VDDQ3 = 3.3V
Pin X2 unconnected
1.65
14
28
V
pF
pF
CIN Input Pin Capacitance
Except X1 and X2
5 pF
COUT
Output Pin Capacitance
6 pF
LIN Input Pin Inductance
7 nH
Notes:
3. X1 input threshold voltage (typical) is VDD/2.
4. The W130 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
14 pF; this includes typical stray capacitance of short PCB traces to crystal.
5. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%,VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU0:5 (Lump Capacitance Test Load = 20 pF)
CPU = 66.6 MHz CPU = 100 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Min. Typ. Max. Unit
tP Period
Measured on rising edge at 1.25V
15
15.5 10
10.5 ns
tH High Time
Duration of clock cycle above 2.0V
5.2
3.0
ns
tL Low Time
Duration of clock cycle below 0.4V
5.0
2.8
ns
tR Output Rise Edge Rate Measured from 0.4V to 2.0V
1 4 1 4 V/ns
tF Output Fall Edge Rate Measured from 2.0V to 0.4V
1 4 1 4 V/ns
tD Duty Cycle
Measured on rising and falling edge at 45
1.25V
55 45
55 %
tJC Jitter, Cycle-to-Cycle Measured on rising edge at 1.25V. Max-
imum difference of cycle time between
two adjacent cycles.
200
200 ps
tSK Output Skew
Measured on rising edge at 1.25V
175 175 ps
fST Frequency Stabiliza- Assumes full supply voltage reached
tion from Power-up
within 1 ms from power-up. Short cycles
(cold start)
exist prior to frequency stabilization.
3
3 ms
Zo AC Output Impedance Average value during switching transi- 15
tion. Used for determining series termi-
nation value.
15 Ω
5
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet W130.PDF ] |
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