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PDF PCF8573T Data sheet ( Hoja de datos )

Número de pieza PCF8573T
Descripción Clock/calendar with Power Fail Detector
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo



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No Preview Available ! PCF8573T Hoja de datos, Descripción, Manual

INTEGRATED CIRCUITS
DATA SHEET
PCF8573
Clock/calendar with Power Fail
Detector
Product specification
Supersedes data of May 1989
File under Integrated Circuits, IC12
1997 Mar 28

1 page




PCF8573T pdf
Philips Semiconductors
Clock/calendar with Power Fail Detector
Product specification
PCF8573
7 FUNCTIONAL DESCRIPTION
7.1 Oscillator
The PCF8573 has an integrated crystal-controlled
oscillator which provides the timebase for the prescaler.
The frequency is determined by a single 32.76 kHz crystal
connected between OSCI and OSCO. A trimmer is
connected between OSCI and VDD.
7.2 Prescaler and time counter
The prescaler provides a 128 Hz signal at the FSET output
for fine adjustment of the crystal oscillator without loading
it. The prescaler also generates a pulse once a second to
advance the seconds counter. The carry of the prescaler
and the seconds counter are available at the outputs SEC,
MIN respectively, and are also readable via the I2C-bus.
The mark-to-space ratio of both signals is 1 : 1. The time
counter is advanced one count by the falling edge of output
signal MIN. A transition from HIGH-to-LOW of output
signal SEC triggers MIN to change state. The time counter
counts minutes, hours, days and months, and provides a
full calendar function which needs to be corrected only
once every four years - to allow for leap-year. Cycle
lengths are shown in Table 1.
7.3 Alarm register
The alarm register is a 24-bit memory. It stores the
time-point for the next setting of the status flag COMP.
Details of writing and reading of the alarm register are
included in the description of the characteristics of the
I2C-bus.
7.4 Comparator
The comparator compares the contents of the alarm
register and the time counter, each with a length of 24 bits.
When these contents are equal the flag COMP will be set
4 ms after the falling edge of MIN. This set condition
occurs once at the beginning of each minute. This
information is latched, but can be cleared by an instruction
via the I2C-bus. A clear instruction may be transmitted
immediately after the flag is set and will be executed. Flag
COMP information is also available at the output COMP.
The comparison may be based upon hours and minutes
only if the internal flag NODA (no date) is set. Flag NODA
can be set and cleared by separate instructions via the
I2C-bus, but it is undefined until the first set or clear
instruction has been received. Both COMP and NODA
flags are readable via the I2C-bus.
Table 1 Cycle length of the time counter
UNIT
minutes
hours
days(1)
months
NUMBER OF BITS
7
6
6
COUNTING CYCLE
00 to 59
00 to 23
01 to 28
01 to 30
01 to 31
5 01 to 12
CARRY FOR
FOLLOWING UNIT
59 00
23 00
28 01
or 29 01
30 01
31 01
12 01
CONTENT OF MONTH
COUNTER
2 (note 1)
2 (note 1)
4, 6, 9, 11
1, 3, 5, 7, 8, 10, 12
Note
1. During February of a leap-year the ‘Time Counter Days’ may be set to 29 by directly writing into it using the ‘execute
address’ function. Leap-years must be tracked by the system software.
1997 Mar 28
5

5 Page





PCF8573T arduino
Philips Semiconductors
Clock/calendar with Power Fail Detector
Product specification
PCF8573
Table 3 MODE-POINTER-word, CONTROL-nibble (bits 8, 7, 6 and 5)
BIT 8 C2 C1 C0
FUNCTION
0 0 0 0 execute address
0 0 0 1 read control/status flags
0 0 1 0 reset prescaler, including seconds counter; without carry for minute counter
0 0 1 1 time adjust, with carry for minute counter (note 1)
0 1 0 0 reset NODA flag
0 1 0 1 set NODA flag
0 1 1 0 reset COMP flag
Note
1. If the seconds counter is below 30 there is no carry. This causes a time adjustment of max. 30 s. From the count
30 there is a carry which adjusts the time by max. +30 s.
Table 4 MODE-POINTER-word, ADDRESS-nibble (bits 4, 3, 2 and 1)
BIT 4 B2 B1 B0
0 0 0 0 time counter hours
0 0 0 1 time counter minutes
0 0 1 0 time counter days
0 0 1 1 time counter months
0 1 0 0 alarm register hours
0 1 0 1 alarm register minutes
0 1 1 0 alarm register days
0 1 1 1 alarm register months
ADDRESSED TO:
At the end of each data word the address bits B1, B0 will be incremented automatically provided the preceding
CONTROL-nibble is set to EXECUTE ADDRESS. There is no carry to B2.
Table 5 shows the placement of the BCD upper and lower digits in the DATA byte for writing into the addressed part of
the time counter and alarm register respectively.
Table 6 shows the acknowledgement response of the clock calendar as a slave receiver.
Table 5 Placement of BCD digits in the DATA byte; note 1
MSB
DATA
UPPER DIGIT
LOWER DIGIT
UD UC UB UA LD LC LB
X X D DDDD
X D D DDDD
X X D DDDD
X X X DDDD
Note
1. ‘X’ is the don’t care bit; ‘D’ is the data bit.
LSB
LA ADDRESSED TO:
D hours
D minutes
D days
D months
1997 Mar 28
11

11 Page







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