PDF vt82c693 Data sheet ( Hoja de datos )

Número de pieza	vt82c693
Descripción	APOLLO PRO-PLUS
Fabricantes	ETC
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Hay una vista previa y un enlace de descarga de vt82c693 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas
No Preview Available ! ZHFRQQHFW 97& $SROOR3UR3OXV 0+] 6LQJOH&KLS6ORW6RFNHW1RUWK%ULGJH IRU'HVNWRSDQG0RELOH3&6\VWHPV ZLWK$3DQG3&, SOXV$GYDQFHG(&&0HPRU\&RQWUROOHU VXSSRUWLQJ6'5$0('2DQG)3 3UHOLPLQDU\5HYLVLRQ 'HFHPEHU 9,$7(&+12/2*,(6,1& 1 page :H &RQQHFW7HFKQRORJLHV ,QF VT82C693 • Advanced High-Performance DRAM Controller − DRAM interface synchronous with host CPU (66/100 MHz) or AGP (66MHz) for most flexible configuration − Concurrent CPU, AGP, and PCI access − Supports FP, EDO, SDRAM and VCM SDRAM memory types − Different DRAM types may be used in mixed combinations − Different DRAM timing for each bank − Dynamic Clock Enable (CKE) control for SDRAM power reduction in high speed systems − Mixed 1M / 2M / 4M / 8M / 16MxN DRAMs − 8 banks up to 1GB DRAMs (128Mb DRAM technology) − Flexible row and column addresses − 64-bit data width only − 3.3V DRAM interface with 5V-tolerant inputs − Programmable I/O drive capability for MA, command, and MD signals − Dual copies of MA signals for improved drive − Optional bank-by-bank ECC (single-bit error correction and multi-bit error detection) or EC (error checking only) for DRAM integrity − Two-bank interleaving for 16Mbit SDRAM support − Two-bank and four bank interleaving for 64Mbit SDRAM support − Supports maximum 8-bank interleave (i.e., 8 pages open simultaneously); banks are allocated based on LRU − Independent SDRAM control for each bank − Seamless DRAM command scheduling for maximum DRAM bus utilization (e.g., precharge other banks while accessing the current bank) − Four cache lines (16 quadwords) of CPU to DRAM write buffers − Four cache lines of CPU to DRAM read prefetch buffers − Read around write capability for non-stalled CPU read − Speculative DRAM read before snoop result − Burst read and write operation − x-2-2-2-2-2-2-2 back-to-back accesses for EDO DRAM from CPU or from DRAM controller − x-1-1-1-1-1-1-1 back-to-back accesses for SDRAM − BIOS shadow at 16KB increment − Decoupled and burst DRAM refresh with staggered RAS timing − CAS before RAS or self refresh • Mobile System Support − Dynamic power down of SDRAM (CKE) − Independent clock stop controls for CPU / SDRAM, AGP, and PCI bus − PCI and AGP bus clock run and clock generator control − VTT suspend power plane preserves memory data − Suspend-to-DRAM and Self-Refresh operation − EDO self-refresh and SDRAM self-refresh power down − 8 bytes of BIOS scratch registers − Low-leakage I/O pads • Built-in NAND-tree pin scan test capability • 3.3V, 0.35um, high speed / low power CMOS process • 35 x 35 mm, 492 pin BGA Package Preliminary Revision 0.3 December 9, 1998 -3- Features 5 Page

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VT82C693A	Single-Chip Slot-1 / Socket-370 North Bridge	VIA

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