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PDF PCF8558U Data sheet ( Hoja de datos )
| Número de pieza | PCF8558U | |
| Descripción | Universal LCD driver for small graphic panels | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
DATA SHEET
PCF8558
Universal LCD driver for small
graphic panels
Objective specification
Supersedes data of 1997 Feb 27
File under Integrated Circuits, IC12
1998 Apr 07
1 page  
Philips Semiconductors
Universal LCD driver for small graphic
panels
Objective specification
PCF8558
FUNCTIONAL DESCRIPTION
LCD bias voltage generator
The intermediate bias voltages for the LCD display are
generated and buffered on-chip. This removes the need
for an external resistor bias chain and significantly reduces
the system power consumption.
Oscillator
The on-chip oscillator provides the clock signal for the
display system. No external components are required and
the OSC pin must be connected to VDD.
External clock
If an external clock is to be used it is input at the OSC pin.
The resulting display frame frequency is given by
fframe = 3-f--O-0---S7---C-2- .
Only in the power-down state is the clock allowed to be
stopped (OSC connected to VSS), otherwise the LCD will
be frozen in a state where a DC voltage is applied to it.
Power-on reset
The on-chip power-on reset block initializes the chip after
power-on or power failure. This is a synchronous reset and
requires 2 oscillator cycles to execute. These oscillator
cycles must be provided from the external clock source if
the internal oscillator is not used. If this is not done, the
device may not respond to command sequences
transmitted via the I2C-bus interface.
Power-down
The chip can be put into power-down mode where all static
currents are switched off (no internal oscillator, no internal
power-on reset, no bias level generation and all LCD
outputs are internally connected to VDD) when
PD = logic 1.
During power-down the information in the RAMs and the
internal chip states are preserved. Instruction execution
during power-down is possible if an externally clock signal
is applied to pad OSC.
Registers
The PCF8558 has one 8-bit register, time shared as a
Command Register (CR) and a Data Register (DR).
The command register stores the command code such as
display on or display off and address information for the
Display Data RAM (DDRAM). Both registers can be written
to but not read from by the system controller.
Address Counter (AC)
The address counter assigns addresses to the DDRAM for
writing and is set by Y2 to Y0 in the command and
X6 to X0 in the address. After a write operation the
address counter is automatically incremented by 1 in
accordance with the V flag.
Display Data RAM (DDRAM)
The PCF8558 contains a 40 × 101-bit static RAM which
stores the display data. The RAM is divided into 5 banks of
101 bytes (5 × 8 × 101 bits). During RAM access, data is
transferred to the RAM via the I2C-bus. There is a direct
correspondence between the X address and the column
output number.
Timing generator
The timing generator produces the various signals
required to drive the internal circuitry. Internal chip
operation is not disturbed by operations on the data buses.
Display control
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The display status (all dots on/off and normal/inverse
video) is set by bits E and D in the command word.
LCD row and column drivers
The PCF8558 contains 40 row and 101 column drivers,
which connect the appropriate LCD bias voltages in
sequence to the display in accordance with the data to be
displayed. Figure 3 illustrates typical waveforms. Unused
outputs should be left unconnected.
The bias voltage levels, V2 to V5, are chosen to give
optimum display contrast for a multiplex rate of 1 : 40.
Table 1 Voltage bias levels
LEVEL
V2
V3
V4
V5
VOLTAGE
0.8635 × (VDD − VLCD)
0.7270 × (VDD − VLCD)
0.2730 × (VDD − VLCD)
0.1365 × (VDD − VLCD)
1998 Apr 07
5
5 Page 
Philips Semiconductors
Universal LCD driver for small graphic
panels
Objective specification
PCF8558
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for bidirectional, two-line communication
between different ICs or modules. The two lines are a
serial data line (SDA) and a serial clock line (SCL) which
must be connected to a positive supply via a pull-up
resistor. Data transfer may be initiated only when the bus
is not busy.
Bit transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this moment will be interpreted as control signals.
START and STOP conditions
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH, is defined as the STOP condition (P).
Acknowledge
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is
unlimited. Each data byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter, whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges must pull down
the SDA line during the acknowledge clock pulse, so that
the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times
must be taken into consideration). A master receiver must
signal the end of a data transmission to the transmitter by
not generating an acknowledge on the last byte that has
been clocked out of the slave. In this event the transmitter
must leave the data line HIGH to enable the master to
generate a stop condition.
System configuration
A device transmitting a message is a 'transmitter', a device
receiving a message is the 'receiver'. The device that
controls the message flow is the 'master' and the devices
which are controlled by the master are the 'slaves'.
handbook, full pagewidth
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Fig.7 Bit transfer.
MBC621
1998 Apr 07
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet PCF8558U.PDF ] | |
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