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PDF UPD703041Y Data sheet ( Hoja de datos )

Número de pieza UPD703041Y
Descripción V850/SV1TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
Fabricantes NEC 
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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
V850/SV1TM
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD703039, 703039Y, 703040, 703040Y, 703041, and 703041Y (collectively known as the V850/SV1) are
products in the low-power series of V850 FamilyTM products, which are NEC’s single-chip microcontrollers for real-
time control.
The V850/SV1 employs the CPU core of the V850 Family, and has on-chip peripheral functions such as large
capacity ROM/RAM, a multi-function timer/counter, serial interface, A/D converter, DMA controller, PWM, and a
Vsync/Hsync separation circuit.
The V850/SV1 not only realizes the low power consumption necessary for applications such as camcorders, but
also extremely high cost performance.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850/SV1 User’s Manual Hardware
: U14462E
V850 Family User’s Manual Architecture : U10243E
FEATURES
{ 10-bit resolution A/D converter: 16 channels
{ Number of instructions: 74
{ Timer/counter
{ Minimum instruction execution time:
24-bit: 2 channels, 16-bit: 2 channels
62.5 ns (@ 16 MHz operation with main system clock)
8-bit: 8 channels
30.5 µs (@ 32.768 kHz operation with subsystem clock) { Watch timer: 1 channel
{ General-purpose registers: 32 bits × 32 registers
{ Watchdog timer: 1 channel
{ Instruction set (signed multiplication, saturation
{ DMA controller: 6 channels
operations, 32-bit shift instructions, bit manipulation { Interrupts and exceptions
instructions, load/store instructions)
Non-maskable interrupt: 2 sources
{ Memory space:
Maskable interrupt
16 MB linear address space
: µPD703039, 703040, 703041 (51 sources)
Memory block allocation function: 2 MB per block
: µPD703039Y, 703040Y, 703041Y (52 sources)
{ External bus: 16-bit multiplexed bus
Software exception: 32 sources
{ Internal memory:
Exception trap: 1 source
µPD703039, 703039Y
{ Serial interface (SIO)
(ROM: 256 KB, RAM: 8 KB)
Asynchronous serial interface (UART)
µPD703040, 703040Y
Clocked serial interface (CSI)
(ROM: 256 KB, RAM: 16 KB)
3-wire variable length serial interface (CSI4)
µPD703041, 703041Y
I2C bus interface (I2C) (µPD703039Y, 703040Y,
(ROM: 192 KB, RAM: 8 KB)
703041Y)
{ I/O lines Total: 151
{ RTP: 8 bits × 2 channels or 4 bits × 4 channels
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U13953EJ1V0DS00 (1st edition)
Date Published March 2000 N CP(K)
Printed in Japan
The mark shows major revised points.
©
2000

1 page




UPD703041Y pdf
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
INTERNAL BLOCK DIAGRAM
NMI
INTP0 to INTP6
INTCP80 to INTCP83,
INTCP90 to INTCP93
INTTCLR8
INTTI8, INTTI9
TI000, TI001,
TI010, TI011
TO0, TO1
TO80, TO81
TI8, TI9
TCLR8
TI2/TO2, TI3/TO3
TI4/TO4, TI5/TO5
TI6/TO6, TI7/TO7
TI10/TO10, TI11/TO11
CSYNCIN
HSOUT0, HSOUT1,
VSOUT
SO0
SI0/SDA0Note 3
SCK0/SCL0Note 3
SO2
SI2/SDA1Note 3
SCK2/SCL1Note 3
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
SO3/TXD1
SI3/RXD1
SCK3/ASCK1
SO4
SI4
SCK4
KR0 to KR7
PWM0 to PWM3
INTC
Timer/counter
16-bit timers
: TM0, TM1
8-bit timers
: TM2 to TM7,
TM10, TM11
24-bit timers
: TM8, TM9
Vsync/Hsync
SIO
CSI0/I2C0Note 4
CSI2/I2C1Note 4
CSI1/UART0
CSI3/UART1
Variable
length CSI4
Key return function
DMAC: 6 ch
PWM
ROM
Note 1
RAM
Note 2
CPU
ROM correction
PC
32-bit barrel
shifter
System
register
General registers
32 bits × 32
Multiplier
16 × 16 32
ALU
Instruction
queue
BCU
HLDRQ
HLDAK
ASTB
DSTB/RD
R/W/WRH
UBEN
LBEN/WRL
WAIT
A16 to A21
AD0 to AD15
Ports
A/D
converter
CG
CLKOUT
CLO
X1
X2
XT1
XT2
RESET
Watch timer
Watchdog timer
RTP
RTP00 to RTP07,
RTP10 to RTP17
RTPTRG0,
RTPTRG1
VDD
VSS
BVDD
BVSS
IC
Notes 1. µPD703039, 703039Y, 703040, 703040Y: 256 KB
µPD703041, 703041Y: 192 KB
2. µPD703039, 703039Y, 703041, 703041Y: 8 KB
µPD703040, 703040Y: 16 KB
3. SDA0, SDA1, SCL0, and SCL1 are valid for the µPD703039Y, 703040Y, and 703041Y only.
4. The I2C function is valid for the µPD703039Y, 703040Y, and 703041Y only.
Preliminary Data Sheet U13953EJ1V0DS00
5

5 Page





UPD703041Y arduino
µPD703039, 703039Y, 703040, 703040Y, 703041, 703041Y
1.2 Non-Port Pins
Pin Name
A16 to A21
AD0 to AD7
AD8 to AD15
ADTRG
ANI0 to ANI7
ANI8 to ANI15
ASCK0
ASCK1
ASTB
AVDD
AVREF
AVSS
BVDD
BVSS
CLKOUT
CLO
CSYNCIN
DSTB
HLDAK
HLDRQ
HSOUT0
HSOUT1
IC
INTCP80 to
INTCP83
INTCP90 to
INTCP93
INTP0 to INTP3
INTP4
INTP5
INTP6
I/O
Output
I/O
Input
Input
Input
Input
Output
Input
Output
Output
Input
Output
Output
Input
Output
Input
Input
Input
PULL
No
No
Yes
No
No
Yes
No
No
No
No
No
No
No
No
No
Yes
Function
Address bus 16 to 21
Address/data multiplexed bus 0 to 15
A/D converter external trigger input
Analog input to A/D converter
Baud rate clock input for UART0 and UART1
External address strobe signal output
Positive power supply for A/D converter and ports used for
alternate functions
Reference voltage input for A/D converter
Ground potential for A/D converter and ports used for alternate
functions
Positive power supply for bus interface and ports used for
alternate functions
Ground potential for bus interface and ports used for alternate
functions
Internal system clock output
CLO output signal
Csync signal input
External data strobe signal output
Bus hold acknowledge output
Bus hold request input
Hsync signal output before revision
Hsync signal output after revision
Internal connection (connect directly to VSS)
External capture input for CC80 to CC83
External capture input for CP90 to CP93
External interrupt request input (digital noise elimination)
External interrupt request input (digital noise elimination)
External interrupt request input (digital noise elimination
supporting remote controller)
Remark PULL: on-chip pull-up resistor
(1/3)
Alternate Function
P60 to P65
P40 to P47
P50 to P57
P05/INTP4
P70 to P77
P80 to P87
P15/SCK1
P25/SCK3
P94
P123
P164
P93/RD
P95
P96
P166
P167
P130 to P133
P140 to P143
P01 to P04
P05/ADTRG
P06/RTPTRG0
P07
Preliminary Data Sheet U13953EJ1V0DS00
11

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