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PDF UPD703037A Data sheet ( Hoja de datos )
| Número de pieza | UPD703037A | |
| Descripción | V850/SB2TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUITS
µPD703037A, 703037AY, 70F3037A, 70F3037AY
V850/SB2TM
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
The µPD703037A, 703037AY, 70F3037A, and 70F3037AY (V850/SB2) are 32-/16-bit single-chip microcontrollers
of the V850 FamilyTM for AV equipment. 32-bit CPU, ROM, RAM, timer/counters, serial interfaces, A/D converter,
DMA controller, and so on are integrated on a single chip.
The µPD70F3037A and 70F3037AY have flash memory in place of the internal mask ROM of the µPD703037A
and 703037AY. Because flash memory allows the program to be written and erased electrically with the device
mounted on the board, these products are ideal for the evaluation stages of system development, small-scale
production, and rapid development of new products.
The µPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, and 70F3035AY with different ROM/RAM
capacity are also available.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850/SB1TM, V850/SB2 User’s Manual Hardware: U13850E
V850 Family User’s Manual Architecture:
U10243E
FEATURES
{ Number of instructions: 74
{ Minimum instruction execution time: 76.9 ns (@ internal 13 MHz operation)
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions,
load/store instructions
{ Memory space: 16 MB linear address space
{ Internal memory ROM: 512 KB (µPD703037A, 703037AY: mask ROM)
512 KB (µPD70F3037A, 70F3037AY: flash memory)
RAM: 24 KB (µPD703037A, 703037AY, 70F3037A, 70F3037AY)
{ Interrupt/exception: µPD703037A, 70F3037A, (external: 8, internal: 33 sources, exception: 1 source)
µPD703037AY, 70F3037AY (external: 8, internal: 34 sources, exception: 1 source)
{ I/O lines Total: 83
{ Timer/counters: 16-bit timer (2 channels: TM0, TM1)
8-bit timer (6 channels: TM2 to TM7)
{ Watch timer: 1 channel
{ Watchdog timer: 1 channel
{ IEBus controller: 1 channel
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14894EJ1V0DS00 (1st edition)
Date Published August 2000 J CP(K)
Printed in Japan
©
2000
1 page  
INTERNAL BLOCK DIAGRAM
µPD703037A, 703037AY, 70F3037A, 70F3037AY
NMI
INTP0 to INTP6
TI00, TI01,
TI10, TI11
TO0, TO1
TI2/TO2
TI3/TO3
TI4/TO4
TI5/TO5
SO0
SI0/SDA0Note 3
SCK0/SCL0Note 3
SO2
SI2/SDA1Note 3
SCK2/SCL1Note 3
SO1/TXD0
SI1/RXD0
SCK1/ASCK0
SO3/TXD1
SI3/RXD1
SCK3/ASCK1
SO4
SI4
SCK4
KR0 to KR7
IETX
IERX
INTC
Timer/counters
16-bit timer
: TM0, TM1
8-bit timer
: TM2 to TM7
SIO
CSI0/I2C0Note 3
CSI2/I2C1Note 3
CSI1/UART0
CSI3/UART1
Variable length
CSI4
Key return
function
DMAC: 6ch
Watch timer
Watchdog timer
IEBus
ROM
Note 1
RAM
Note 2
CPU
ROM
PC correction
32-bit barrel
shifter
System
registers
General registers
32 bits × 32
Multiplier
16 × 16 → 32
ALU
Instruction
queue
BCU
HLDRQ (P96)
HLDAK (P95)
ASTB (P94)
DSTB/RD (P93)
R/W/WRH (P92)
UBEN (P91)
LBEN/WRL (P90)
WAIT (P110)
A1 to A12
(P100 to P107, P110 to P113)
A13 to A15 (P34 to P36)
A16 to A21 (P60 to P65)
AD0 to AD15
(P40 to P47, P50 to P57)
Ports
RTP
A/D
converter
CG
CLKOUT
X1
X2
XT1
XT2
RESET
3.0 V
Regulator
VDD
VSS
BVDD
BVSS
EVDD
EVSS
VPPNote 4
ICNote 5
Notes 1.
2.
3.
4.
5.
µPD703037A, 703037AY: 512 KB (mask ROM)
µPD70F3037A, 70F3037AY: 512 KB (flash memory)
µPD703037A, 703037AY, 70F3037A, 70F3037AY: 24 KB
I2C bus interface and SDAn and SCLn pins (n = 0, 1) are available only in the µPD703037AY and
70F3037AY.
µPD70F3037A, 70F3037AY
µPD703037A, 703037AY
Data Sheet U14894EJ1V0DS00
5
5 Page 
µPD703037A, 703037AY, 70F3037A, 70F3037AY
Pin Name
I/O PULL
Function
IERX
Input
Yes IEBus data input
IETX
Output
IEBus data output
INTP0
Input
Yes External interrupt request input (analog noise elimination)
INTP1
INTP2
INTP3
INTP4
Input
Yes External interrupt request input (digital noise elimination)
INTP5
INTP6
Input
Yes External interrupt request input (digital noise elimination
supporting remote controller)
KR0
Input
Yes Key return input
KR1
KR2
KR3
KR4
KR5
KR6
KR7
LBEN
Output No External data bus’s low-order byte enable output
NMI
Input
Yes Non-maskable interrupt request input
RD Output No Read strobe output
REGC
− − Regulator output stabilization capacitance connection
RESET
Input
− System reset input
RTP0
Output Yes Real-time output port
RTP1
RTP2
RTP3
RTP4
RTP5
RTP6
RTP7
RTPTRG
Input
Yes Real-time output port external trigger input
R/W Output No External read/write status output
RXD0
Input
Yes Serial receive data input for UART0 and UART1
RXD1
Remark PULL: On-chip pull-up resistor
(2/4)
Alternate Function
P104/RTP4/A9/KR4
P105/RTP5/A10/KR5
P01
P02
P03
P04
P05/ADTRG
P06/RTPTRG
P07
P100/RTP0/A5
P101/RTP1/A6
P102/RTP2/A7
P103/RTP3/A8
P104/RTP4/A9/IERX
P105/RTP5/A10/IETX
P106/RTP6/A11
P107/RTP7/A12
P90/WRL
P00
P93/DSTB
−
−
P100/KR0/A5
P101/KR1/A6
P102/KR2/A7
P103/KR3/A8
P104/KR4/A9/IERX
P105/KR5/A10/IETX
P106/KR6/A11
P107/KR7/A12
P06/INTP5
P92/WRH
P13/SI1
P23/SI3
Data Sheet U14894EJ1V0DS00
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet UPD703037A.PDF ] | |
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