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PDF UPD703034AYGC Data sheet ( Hoja de datos )

Número de pieza UPD703034AYGC
Descripción V850/SB2TM 32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
Fabricantes NEC 
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703034A, 703034AY, 703035A,
703035AY, 70F3035A, 70F3035AY
V850/SB2TM
32-/16-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, and 70F3035AY (V850/SB2) are 32-/16-bit
single-chip microcontrollers of the V850 FamilyTM for AV equipment. 32-bit CPU, ROM, RAM, timer/counters, serial
interfaces, A/D converter, DMA controller, and so on are integrated on a single chip.
The µPD70F3035A and 70F3035AY have flash memory in place of the internal mask ROM of the µPD703035A
and 703035AY. Because flash memory allows the program to be written and erased electrically with the device
mounted on the board, these products are ideal for the evaluation stages of system development, small-scale
production, and rapid development of new products.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V850/SB1TM, V850/SB2 User’s Manual Hardware: U13850E
V850 Family User’s Manual Architecture:
U10243E
FEATURES
{ Number of instructions: 74
{ Minimum instruction execution time: 76.9 ns (@ internal 13 MHz operation)
{ General-purpose registers: 32 bits × 32 registers
{ Instruction set: Signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions,
load/store instructions
{ Memory space: 16 MB linear address space
{ Internal memory ROM: 128 KB (µPD703034A, 703034AY: mask ROM)
256 KB (µPD703035A, 703035AY: mask ROM)
256 KB (µPD70F3035A, 70F3035AY: flash memory)
RAM: 12 KB (µPD703034A, 703034AY)
16 KB (µPD703035A, 703035AY, 70F3035A, 70F3035AY)
{ Interrupt/exception: µPD703034A, 703035A, 70F3035A (external: 8, internal: 32 sources, exception: 1 source)
µPD703034AY, 703035AY, 70F3035AY (external: 8, internal: 33 sources, exception: 1 source)
{ I/O lines Total: 83
{ Timer/counters: 16-bit timer (2 channels: TM0, TM1)
8-bit timer (6 channels: TM2 to TM7)
{ Watch timer: 1 channel
{ Watchdog timer: 1 channel
{ IEBus controller: 1 channel
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. U14780EJ1V0DS00 (1st edition)
Date Published May 2000 N CP(K)
Printed in Japan
©
2000

1 page




UPD703034AYGC pdf
µPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY
PIN IDENTIFICATION
A1 to A21:
AD0 to AD15:
ADTRG:
ANI0 to ANI11:
ASCK0, ASCK1:
ASTB:
AVDD:
AVREF:
AVSS:
BVDD:
BVSS:
CLKOUT:
DSTB:
EVDD:
EVSS:
HLDAK:
HLDRQ:
IC:
IERX:
IETX:
INTP0 to INTP6:
KR0 to KR7:
LBEN:
NMI:
P00 to P07:
P10 to P15:
P20 to P27:
P30 to P37:
P40 to P47:
P50 to P57:
P60 to P65:
Address Bus
Address/Data Bus
AD Trigger Input
Analog Input
Asynchronous Serial Clock
Address Strobe
Analog Power Supply
Analog Reference Voltage
Analog Ground
Power Supply for Bus Interface
Ground for Bus Interface
Clock Output
Data Strobe
Power Supply for Port
Ground for Port
Hold Acknowledge
Hold Request
Internally Connected
IEBus Receive Data
IEBus Transmit Data
Interrupt Request from Peripherals
Key Return
Lower Byte Enable
Non-Maskable Interrupt Request
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
P70 to P77:
P80 to P83:
P90 to P96:
P100 to P107:
P110 to P113:
RD:
REGC:
RESET:
RTP0 to RTP7:
RTPTRG:
R/W:
RXD0, RXD1:
SCK0 to SCK4:
SCL0, SCL1:
SDA0, SDA1:
SI0 to SI4:
SO0 to SO4:
TI00, TI01, TI10, :
TI11, TI2 to TI5
TO0 to TO5:
TXD0, TXD1:
UBEN:
VDD:
VPP:
VSS:
WAIT:
WRH:
WRL:
X1, X2:
XT1, XT2:
Port 7
Port 8
Port 9
Port 10
Port 11
Read
Regulator Clock
Reset
Real-time Output Port
RTP Trigger Input
Read/Write Status
Receive Data
Serial Clock
Serial Clock
Serial Data
Serial Input
Serial Output
Timer Input
Timer Output
Transmit Data
Upper Byte Enable
Power Supply
Programming Power Supply
Ground
Wait
Write Strobe High Level Data
Write Strobe Low Level Data
Crystal for Main Clock
Crystal for Sub-clock
Data Sheet U14780EJ1V0DS00
5

5 Page





UPD703034AYGC arduino
µPD703034A, 703034AY, 703035A, 703035AY, 70F3035A, 70F3035AY
2.2 Non-Port Pins
Pin Name
I/O PULL
Function
(1/4)
Alternate Function
A1 Output Yes Low-order address bus used for external memory expansion P110/WAIT
A2 P111
A3 P112
A4 P113
A5 P100/RTP0/KR0
A6 P101/RTP1/KR1
A7 P102/RTP2/KR2
A8 P103/RTP3/KR3
A9 P104/RTP4/KR4/IERX
A10 P105/RTP5/KR5/IETX
A11 P106/RTP6/KR6
A12 P107/RTP7/KR7
A13 P34/TO0/SCK4
A14 P35/TO1
A15 P36/TO4/TI4
A16 to A21
Output No High-order address bus used for external memory expansion P60 to P65
AD0 to AD7
AD8 to AD15
I/O No 16-bit multiplexed address/data bus used for external memory P40 to P47
expansion
P50 to P57
ADTRG
Input
Yes A/D converter external trigger input
P05/INTP4
ANI0 to ANI7
Input
No Analog input to A/D converter
P70 to P77
ANI8 to ANI11
P80 to P83
ASCK0
Input
Yes Baud rate clock input for UART0
P15/SCK1
ASCK1
Baud rate clock input for UART1
P25/SCK3
ASTB
Output No External address strobe output
P94
AVDD
AVREF
Input
Positive power supply for A/D converter and alternate port
Reference voltage input for A/D converter
AVSS
− − Ground potential for A/D converter and alternate port
BVDD
BVSS
− − Positive power supply for bus interface and alternate port
− − Ground potential for bus interface and alternate port
CLKOUT
Output Internal system clock output
DSTB
Output No External data strobe output
P93/RD
EVDD
− − Positive power supply for I/O ports and alternate-function pins
(except bus interface alternate port)
EVSS
− − Ground potential for I/O ports and alternate-function pins
(except bus interface alternate port)
HLDAK
Output No Bus hold acknowledge output
P95
HLDRQ
Input
No Bus hold request input
P96
IC − − Internally connected
(µPD703034A, 703034AY, 703035A, 703035AY only)
Remark PULL: On-chip pull-up resistor
Data Sheet U14780EJ1V0DS00
11

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