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PDF UPD6600A Data sheet ( Hoja de datos )
| Número de pieza | UPD6600A | |
| Descripción | 4-BIT SINGLE-CHIP MICROCONTROLLER FOR REMOTE CONTROL TRANSMISSION | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD6124A, 6600A
4-BIT SINGLE-CHIP MICROCONTROLLER
FOR REMOTE CONTROL TRANSMISSION
DESCRIPTION
The µPD6124A and 6600A are 4-bit single-chip microcontrollers for infrared remote controllers for TVs, VCRs,
stereos, cassette decks, air conditions, etc.
These microcontrollers consist of ROM, RAM, a 4-bit parallel-processing ALU, a programmable timer, key input/
output ports, and transmit output ports. Functioning is controlled by a program.
A one-time PROM, model µPD61P24, to which a program can be written only once is also available. This one-time
PROM is ideal for evaluation of programs running in a µPD6124A or 6600A, and for small-scale production of such
systems.
FEATURES
• Transmitter for programmable infrared remote control-
ler
• 19 types of instructions
• Instruction execution time: 17.6 µs (with 455-kHz ce-
ramic resonator)
• Program memory (ROM) capacity
• µPD6124A: 1002 × 10 bits
• µPD6600A: 512 × 10 bits
• Data memory (RAM) capacity: 32 × 5 bits
• 9-bit programmable timer: 1 channel
• I/O pins (KI/O): 8 pins
• Input pins (KI): 4 pins
• Serial input pins (S-IN): 1 pin
• Transmission-in-progress indication pin (S-OUT): 1
pin
• Transmit carrier frequency (REM)
fOSC/12, fOSC/8
• Standby operation (HALT/STOP mode)
• Low power consumption
• Current consumption in STOP mode (TA = 25°C)
• Low-voltage operation
µPD6124A: VDD = 2.2 to 5.5 V
µPD6600A: VDD = 2.2 to 3.6 V
Caution To use the NEC transmission format, ask NEC to supply the custom code.
Do not use R0 when using a register as an operand of the branch instruction.
The information in this document is subject to change without notice.
Document No. U12391EJ5V0DS00 (5th edition)
(Previous No. IC-1927)
Date Published June 1997 N
Printed in Japan
The mark shows major revised points.
© 1989
1 page  
µPD6124A, 6600A
3. PROGRAM MEMORY (ROM) ……… 512 STEPS × 10 BITS : µPD6600A
1002 STEPS × 10 BITS : µPD6124A
The program memory (ROM) is configured in 10 bits steps. It is addressed by the program counter.
Program and table data are stored in the program memory.
Figure 3-1. Program Memory Map
000H
0FFH
100H
1FFH
(a) µPD6600A
000H
0FFH
100H
1FFH
200H
2FFH
300H
3E9H
3EAH
3FFH
(b) µPD6124A
Test program
area
4. DATA MEMORY (RAM) ……… 32 WORDS × 5 BITS
The data memory is a RAM of 32 words × 5 bits. The data memory stores processing data. In some cases, the
data memory is processed in 8-bit units. R0 may be used as the data pointer for the ROM.
After power application, the RAM will be undefined. The RAM retains the previous data on reset.
Figure 4-1. Data Memory Organization
10
R0
...
0
0
1
1
0
0
1
1
RB
RC SP–3
...
SP–2
SP–1
SP–0
RF
Caution
Avoid using the RAM areas RD, RE, and RF in a CALL routine as much as possible because these areas
are also used as stack memory areas (to prevent program hang-up in case the value of the SP is
destroyed due to some reason such as noise).
When using these RAM areas as general-purpose RAM areas, be sure to include stack pointer
checking in the main routine.
5
5 Page 
µPD6124A, 6600A
11.5 S-OUT PIN
By going low whenever the carrier frequency is output from the REM pin, the S-OUT pin indicates that communication
is in progress.
The S-OUT pin is CMOS output.
The S-OUT pin goes high on reset.
11.6 S-IN PIN (D0 BIT OF P1)
To input serial data, use the S-IN pin. When control register (P1) is set to serial input mode, the S-IN pin is connected
as an input to the LSB of the accumulator; the S-IN pin can be pulled down to the VSS level by a mask option from within
the LSI. In this state, if the rotate-left accumulator instruction (RL A) is executed, the data on the S-IN pin is copied
to the LSB of the accumulator.
If the control register is released from serial input mode, the S-IN pin goes into a high-impedance state, but no through
current flows internally.
When the RL A instruction is executed, the MSB is copied to the LSB.
At reset (all cleared), the S-IN pin goes into a high-impedance state.
Caution The µPD6123 is not provided with an S-IN pin.
Figure 11-3. Configuration of the S-IN Pin
CY A 3 A 2 A 1 A 0
S-IN
Control register
11
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