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PDF UPD4990AC Data sheet ( Hoja de datos )

Número de pieza UPD4990AC
Descripción SERIAL I/O CALENDAR & CLOCK CMOS LSI
Fabricantes NEC 
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No Preview Available ! UPD4990AC Hoja de datos, Descripción, Manual

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4990A
SERIAL I/O CALENDAR & CLOCK
CMOS LSI
The µPD4990A is a CMOS LSI developed to input/output calendar & clock data serially to/from the micro computer.
The crystal frequency is 32.768 kHz and the data items included are time, minute, second, year, month, day, and
week.
FEATURES
Built-in counters for time (hour, minute, and second) and date (year, month, day, and week)
Leap years are adjusted automatically.
Data is represented in BCD notation (except months in hexadecimal notation) and input/output serially.
Commands can be set by inputting serial data.
Selective timing pulses (TPs) are 64 Hz, 256 Hz, 2 048 Hz, and 4 096 Hz and selective output intervals are 1, 10,
30, and 60 seconds.
ORDERING INFORMATION
PART No.
µPD4990AC
µPD4990AG
PACKAGE
14-pin plastic DIP (300 mil)
16-pin plastic SOP (300 mil)
CONNECTION DIAGRAM (Top View)
C2 1
14 VDD (+)
C1 2
13 XTAL
C0 3
12 XTAL
STB 4
11 OUT ENBL
CS 5
10 TP
DATA IN 6
9 DATA OUT
GND 7
(VSS)
8 CLK
µ PD4990AC
C2 1
16 VDD (+)
C1 2
15 XTAL
C0 3
14 XTAL
NC 4
13 NC
STB 5
12 OUT ENBL
CS 6
11 TP
DATA IN 7
10 DATA OUT
GND 8
(VSS)
9 CLK
µ PD4990AG
NC: NO CONNECTION
Document No. IC-1755 (1st edition)
Date Published March 1997 P
Printed in Japan
© 1989

1 page




UPD4990AC pdf
µPD4990A
TERMINALS
Input terminals
° DATA IN
° CLK
° C0, C1, C2
° STB
° CS
° OUT ENBL
Data input of 40-/52-bit shift register
Shift clock input of 40-/52-bit shift register
Command input (3 bit)
Strobe input
Chip select input (Prohibits CLK & STB)
Output control input (Makes the DATA OUT high impedance by inputting low level).
Output terminals (N-channel Open Drain)
° DATA OUT
° TP
Data output of 40-/52-bit shift register
Timing pulse output
Oscillation terminals
° XTAL
° XTAL
Oscillation inverter input (OSC IN)
Oscillation inverter output (OSC OUT)
Power supply terminals
° VDD
° GND (VSS)
Plus power supply
Common line
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UPD4990AC arduino
µPD4990A
TIMING DIAGRAM FOR SETTING COMMANDS (C0', C1', C2', C3')
Figure 2.
DATA
IN
CLK
STB
VIH VIH
C0' C1' C2' C3'
VIL VIL
tDSU
tDHLD
VIH VIH
VIL VIL
tHLD
VIH
VIL
tSTB
NEW COMMAND
VALID
Other than time read mode
OLD MODE
Time read mode
OLD MODE
td1
NEW MODE
td2
NEW MODE
VDD VSS = 2.0 V
tDSU = 1 µs MIN.
tDHLD = 1 µs MIN.
tHLD = 1 µs MIN.
tSTB = 1 µs MIN.
td1 = 1 µs MAX. (Other than time read mode)
td2 = 20 µs MAX. (Time read mode)
Note: Command (C2, C1, C0) is set to (1, 1, 1)
CS = "H"
A mode is latched by STB and held until another mode in the same group is set.
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