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PDF UPD488448 Data sheet ( Hoja de datos )

Número de pieza UPD488448
Descripción 128 M-bit Direct Rambus DRAM
Fabricantes NEC 
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD488448 for Rev. P
128 M-bit Direct Rambus™ DRAM
Description
The Direct Rambus DRAM (Direct RDRAM) is a general purpose high-performance memory device suitable for
use in a broad range of applications including computer memory, graphics, video, and any other application where
high bandwidth and low latency are required.
The µPD488448 is 128M-bit Direct Rambus DRAM (RDRAM®), organized as 8M words by 16 bits.
The use of Rambus Signaling Level (RSL) technology permits 600 MHz to 800 MHz transfer rates while using
conventional system and board design technologies. Direct RDRAM devices are capable of sustained data transfers
at 1.25 ns per two bytes (10 ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and data buses with independent row and column control
yield over 95% bus efficiency. The Direct RDRAM’s thirty-two banks support up to four simultaneous transactions.
System oriented features for mobile, graphics and large memory systems include power management, byte
masking.
The µPD488448 is offered in a CSP horizontal package suitable for desktop as well as low-profile add-in card and
mobile applications. Direct RDRAMs operate from a 2.5 volt supply.
Features
Highest sustained bandwidth per DRAM device
- 1.6 GB/s sustained data transfer rate
- Separate control and data buses for maximized efficiency
- Separate row and column control buses for easy scheduling and highest performance
- 32 banks: four transactions can take place simultaneously at full bandwidth data rates
Low latency features
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
Advanced power management:
- Multiple low power states allows flexibility in power consumption versus time to transition to active state
- Power-down self-refresh
Overdrive current mode
Organization: 1 Kbyte pages and 32 banks, x 16
Uses Rambus Signaling Level (RSL) for up to 800 MHz operation
Package : 62-pin TAPE FBGA (µBGA®) and 62-pin PLASTIC FBGA (D2BGA(Die Dimension Ball Grid Array) )
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14837EJ3V0DS00 (3rd edition)
Date Published August 2000 NS CP (K)
Printed in Japan
The mark shows major revised points.
©
2000

1 page




UPD488448 pdf
µPD488448 for Rev. P
Pin Description
Signal
Input / Output Type #pins
Description
SIO0, SIO1
CMD
SCK
Input / Output CMOS Note1 2
Input
CMOS Note1
1
Input
CMOS Note1
1
Serial input/output. Pins for reading from and writing to the control registers using
a serial access protocol. Also used for power management.
Command input. Pins used in conjunction with SIO0 and SIO1 for reading from
and writing to the control registers. Also used for power management.
Serial clock input. Clock source used for reading from and writing to the control
registers.
VDD 10 Supply voltage for the RDRAM core and interface logic.
VDDa 1 Supply voltage for the RDRAM analog circuitry.
VCMOS
2 Supply voltage for CMOS input/output pins.
GND
13 Ground reference for RDRAM core and interface.
GNDa
1 Ground reference for RDRAM analog circuitry.
DQA7..DQA0 Input / Output RSL Note2
CFM
Input
RSL Note2
CFMN
Input
RSL Note2
8 Data byte A. Eight pins which carry a byte of read or write data between the
Channel and the RDRAM.
1 Clock from master. Interface clock used for receiving RSL signals from the
Channel. Positive polarity.
1 Clock from master. Interface clock used for receiving RSL signals from the
Channel. Negative polarity.
VREF 1 Logic threshold reference voltage for RSL signals.
CTMN
Input
RSL Note2
CTM
Input
RSL Note2
RQ7..RQ5 or
ROW2..ROW0
RQ4..RQ0 or
COL4..COL0
DQB7..DQB0
Input
RSL Note2
Input
RSL Note2
Input / Output RSL Note2
1 Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Negative polarity.
1 Clock to master. Interface clock used for transmitting RSL signals to the Channel.
Positive polarity.
3 Row access control. Three pins containing control and address information for
row accesses.
5 Column access control. Five pins containing control and address information for
column accesses.
8 Data byte B. Eight pins which carry a byte of read or write data between the
Channel and the RDRAM.
NC 2 These pins aren’t connected to inside of the chip.
Total pin count per package
62
Notes 1.All CMOS signals are high-true ; a high voltage is a logic one and a low voltage is logic zero.
2.All RSL signals are low-true ; a low voltage is a logic one and a high voltage is logic zero.
Data Sheet M14837EJ3V0DS00
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UPD488448 arduino
µPD488448 for Rev. P
2. Packet Format
Figure 2-1 shows the formats of the ROWA and ROWR packets on the ROW pins. Table 2-1 describes the fields
which comprise these packets. DR4T and DR4F bits are encoded to contain both the DR4 device address bit and a
framing bit which allows the ROWA or ROWR packet to be recognized by the RDRAM.
The AV (ROWA/ROWR packet selection) bit distinguishes between the two packet types. Both the ROWA and
ROWR packet provide a five bit device address and a four bit bank address. An ROWA packet uses the remaining
bits to specify a nine bit row address, and the ROWR packet uses the remaining bits for an eleven bit opcode field.
Note the use of the “RsvX” notation to reserve bits for future address field extension.
Figure 2-1 also shows the formats of the COLC, COLM, and COLX packets on the COL pins. Table 2-2 describes
the fields which comprise these packets.
The COLC packet uses the S (Start) bit for framing. A COLM or COLX packet is aligned with this COLC packet, and
is also framed by the S bit.
The 23 bit COLC packet has a five bit device address, a four bit bank address, a six bit column address, and a four
bit opcode. The COLC packet specifies a read or write command, as well as some power management commands.
The remaining 17 bits are interpreted as a COLM (M=1) or COLX (M=0) packet. A COLM packet is used for a
COLC write command which needs bytemask control. The COLM packet is associated with the COLC packet from a
time tRTR earlier. An COLX packet may be used to specify an independent precharge command. It contains a five bit
device address, a four bit bank address, and a five bit opcode. The COLX packet may also be used to specify some
housekeeping and power management commands. The COLX packet is framed within a COLC packet but is not
otherwise associated with any other packet.
Field
DR4T, DR4F
DR3..DR0
BR4..BR0
AV
R8..R0
ROP10..ROP0
Table 2-1 Field Description for ROWA Packet and ROWR Packet
Description
Bits for framing (recognizing) a ROWA or ROWR packet. Also encodes highest device address bit.
Device address for ROWA or ROWR packet.
Bank address for ROWA or ROWR packet. RsvB denotes bits ignored by the RDRAM.
Selects between ROWA packet (AV=1) and ROWR packet (AV=0).
Row address for ROWA packet. RsvR denotes bits reserved for future row address extension.
Opcode field for ROWR packet. Specifies precharge, refresh, and power management functions.
Field
S
DC4..DC0
BC4..BC0
C5..C0
COP3..COP0
M
MA7..MA0
MB7..MB0
DX4..DX0
BX4..BX0
XOP4..XOP0
Table 2-2 Field Description for COLC Packet, COLM Packet, and COLX Packet
Description
Bit for framing (recognizing) a COLC packet, and indirectly for framing COLM and COLX packets.
Device address for COLC packet.
Bank address for COLC packet. RsvB denotes bits reserved for future extension (controller drivers 0's).
Column address for COLC packet. RsvC denotes bits ignored by the RDRAM.
Opcode field for COLC packet. Specifies read, write, precharge, and power management functions.
Selects between COLM packet (M=1) and COLX packet (M=0).
Bytemask write control bits. 1=write, 0=no-write. MA0 controls the earliest byte on DQA7..0.
Bytemask write control bits. 1=write, 0=no-write. MB0 controls the earliest byte on DQB7..0.
Device address for COLX packet.
Bank address for COLX packet. RsvB denotes bits reserved for future extension (controller drivers 0's).
Opcode field for COLX packet. Specifies precharge, IOL control, and power management functions.
Data Sheet M14837EJ3V0DS00
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