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PDF UPD4702C Data sheet ( Hoja de datos )
| Número de pieza | UPD4702C | |
| Descripción | INCREMENTAL ENCODER 8-BIT UP/DOWN COUNTER CMOS INTEGRATED CIRCUITS | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD4702
INCREMENTAL ENCODER 8-BIT UP/DOWN COUNTER
CMOS INTEGRATED CIRCUITS
DESCRIPTION
The µPD4702 is 8-bit up/down counters for an incremental encoder. Two-phase (A, B) incremental input signals
are phase-differentiated, and on each signal edge, an up-count is executed if the A phase is leading, or a down-count
if the B phase is leading. Eight-bit count data is output in real time. A carry output and borrow output are also
provided for counter overflow and underflow.
The µPD4704 is also available; use of these enables the count width to be extended.
FEATURES
• Incremental inputs (A, B)
• On-chip phase discrimination circuit (up-count mode
when the phase order is A → B, down-count mode
when B → A) 4-multiplication count method
• On-chip edge detection circuit
• 8-bit up/down counter latch output o Carry output,
borrow output
• Count data output controllable (3-state output)
• CMOS, single +5 V power supply
ORDERING INFORMATION
Part Number
µPD4702C
µPD4702G
Package
20-pin plastic DIP
20-pin plastic SOP
(300 mil)
(300 mil)
PIN CONFIGURATION (Top View)
Reset
A
B
NC
CD0
CD1
CD2
CD3
NC
VSS
1
2
3
4
5
6
7
8
9
10
20 VDD
19 Carry
18 Borrow
17 STB
16 OE
15 CD7
14 CD6
13 CD5
12 CD4
11 NC
PIN NAMES
A
2-phase incremental signal inputs
B
Reset : Counter reset input
STB : Latch strobe signal input
OE : Output control signal input
CD0-7 : Count data outputs
Carry : Carry pulse output
Borrow : Borrow pulse output
Document No. IC-3304A (2nd edition)
(O. D. No. IC-5403A)
Date Published April 1997 P
Printed in Japan
© 11999934
1 page  
µPD4702
2. OPERATING PRECAUTIONS
As the µPD4702 incorporates an 8-bit counter, a large transient current flows in the case of a count value which
changes all the bits (such as 00H ↔ 0FFH or 7FH ↔ 080H). This will cause misoperation unless the impedance of the
power supply line is sufficiently low. It is therefore recommended that a decoupling capacitor (of around 0.1 µF)
be connected between VDD and VSS right next to the IC as shown in Fig. 3.
Fig. 3 Decoupling Capacitor
C
VDD
+5 V
µPD4702
C : 0.1 µF tantalum electrolytic laminated
ceramic capacitor, etc.
VSS
Also, if a pulse shorter than the phase difference time tSAB (70 ns) is input to the A/ B phase inputs, this will result
in a miscount. Therefore, if this kind of pulse is to be input because of encoder bounds, etc., a filter should be inserted
in the A & B phase inputs.
Fig. 4 A & B Phase Input Pulses
A Phase (or B Phase)
B Phase (or A Phase)
PW
If a pulse such that PW < 70 ns is input
in the A or B phase, there is a danger of
a miscount.
If PW is at 70 ns or more, the count value remains the same before and after pulse input. (UP count → DOWN
count or DOWN count → UP count is implemented, and therefore the the result is no change in the count value.)
5
5 Page 
20PIN PLASTIC DIP (300 mil)
20
11
µPD4702
1
I
J
10
A
P
K
L
H
G
F
D NM
C
B
NOTES
1) Each lead centerline is located within 0.25 mm (0.01 inch) of
its true position (T.P.) at maximum material condition.
2) ltem "K" to center of leads when formed parallel.
MR
ITEM MILLIMETERS INCHES
A 25.40 MAX. 1.000 MAX.
B 1.27 MAX. 0.050 MAX.
C 2.54 (T.P.) 0.100 (T.P.)
D
0.50±0.10
0.020
+0.004
–0.005
F 1.1 MIN.
0.043 MIN.
G 3.5±0.3
0.138±0.012
H
0.51 MIN.
0.020 MIN.
I 4.31 MAX. 0.170 MAX.
J 5.08 MAX. 0.200 MAX.
K 7.62 (T.P.) 0.300 (T.P.)
L 6.4
0.252
M
0.25
+0.10
–0.05
0.010
+0.004
–0.003
N 0.25
0.01
P 0.9 MIN.
0.035 MIN.
R 0~15 °
0~15°
P20C-100-300A,C-1
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet UPD4702C.PDF ] | |
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