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PDF UPD3788D Data sheet ( Hoja de datos )
| Número de pieza | UPD3788D | |
| Descripción | 7300 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD3788
7300 PIXELS × 3 COLOR CCD LINEAR IMAGE SENSOR
The µPD3788 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which
changes optical images to electrical signal and has the function of color separation.
The µPD3788 has 3 rows of 7300 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge
transfer register, which transfers the photo signal electrons of 7300 pixels separately in odd and even pixels.
Moreover, the spectral response characteristics of the µPD3788 is modified from the previous device µPD3728 to be
suitable for Xe-lamp. Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers and so on.
FEATURES
• Valid photocell : 7300 pixels × 3
• Photocell pitch : 10 µm
• Photocell size : 10 × 10 µm2
• Line spacing
: 40 µm (4 lines) Red line-Green line, Green line-Blue line
• Color filter
: Primary colors (red, green and blue), pigment filter (with light resistance 107 lx•hour)
• Resolution
: 24 dot/mm (600 dpi) A3 (297 × 420 mm) size (shorter side)
• Drive clock level : CMOS output under 5 V operation
• Data rate
: 40 MHz MAX. (20 MHz/1 output)
• Output type
: 2 outputs in phase/color
• Power supply : +12 V
• On-chip circuits : Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
µPD3788D CCD linear image sensor 36-pin ceramic DIP (15.24 mm (600))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S14664EJ1V0DS00(1st edition)
Date published June 2000 N CP(K)
Printed in Japan
©
2000
1 page  
µPD3788
ABSOLUTE MAXIMUM RATINGS (TA = +25 °C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Reset feed-through level clamp clock voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
Symbol
VOD
Vφ1, Vφ1L, Vφ10, Vφ2, Vφ20
VφRB
VφCLB
VφTG1 to VφTG3
TA
Tstg
Ratings
–0.3 to +15
–0.3 to +8
–0.3 to +8
–0.3 to +8
–0.3 to +8
–25 to +60
–40 to +100
Unit
V
V
V
V
V
°C
°C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = +25 °C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Reset feed-through level clamp clock high level
Reset feed-through level clamp clock low level
Transfer gate clock high levelNote
Symbol
VOD
Vφ1H, Vφ1LH, Vφ10H, Vφ2H, Vφ20H
Vφ1L, Vφ1LL, Vφ10L, Vφ2L, Vφ20L
VφRBH
VφRBL
VφCLBH
VφCLBL
VφTG1H to VφTG3H
Transfer gate clock low level
Data rate
VφTG1L to VφTG3L
2fφRB
MIN.
11.4
4.5
–0.3
4.5
–0.3
4.5
–0.3
4.5
–0.3
–
TYP.
12.0
5.0
0
5.0
0
5.0
0
Vφ1H
(Vφ10H)
0
2
MAX.
12.6
5.5
+0.5
5.5
+0.5
5.5
+0.5
Vφ1H
(Vφ10H)
+0.5
40
Unit
V
V
V
V
V
V
V
V
V
MHz
Note When Transfer gate clock high level (VφTG1H to VφTG3H) is higher than Shift register clock high level (Vφ1H (Vφ10H)),
Image lag can increase.
Remark Pin 9 (φ10) and pin 28 (φ20) should be open to decrease the influence of input clock noise to output signal
waveform, in case of operating at low or middle speed range; data rate under 24 MHz or so.
Data Sheet S14664EJ1V0DS00
5
5 Page 
TIMING CHART 3 (Bit clamp mode, for each color)
φ TG1 to φ TG3
φ 1 (φ10)
t13
90 %
10 %
t15
90 %
φ 2 (φ20)
t12
φ 1L
φ RB
φ CLB
Note 1
µPD3788
t14
t16
90 %
t11
90 %
Symbol
t11
t12
t13, t14
t15, t16
MIN.
–5Note 2
3000
0
900
TYP.
+50
10000
50
1000
MAX.
Unit
ns
ns
ns
ns
Notes 1. Input the φRB and φCLB pulses continuously during this period, too.
2. MIN. of t11 shows that the φ1L and φCLB overlap each other.
φ 1L
φ CLB
90 %
t11
90 %
φ1 (φ10), φ2 (φ20) cross points
φ1L, φ2 (φ20) cross points
φ1 (φ10)
φ 2 (φ 20)
φ 2 (φ 20)
2 V or more
2 V or more
φ 1L
2 V or more
0.5 V or more
Remark Adjust cross points (φ1 (φ10), φ2 (φ20)) and (φ1L, φ2 (φ20)) with input resistance of each pin.
Data Sheet S14664EJ1V0DS00
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet UPD3788D.PDF ] | |
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