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PDF UPD3739D Data sheet ( Hoja de datos )

Número de pieza UPD3739D
Descripción 5000 PIXELS CCD LINEAR IMAGE SENSOR
Fabricantes NEC 
Logotipo NEC Logotipo



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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD3739
5000 PIXELS CCD LINEAR IMAGE SENSOR
The µPD3739 is a CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical
signal.
The µPD3739 is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers
the photo signal electrons of 5000 pixels separately in odd and even pixels. It is developed as the higher sensitivity
version of the previous device, the µPD35H71A. It is suitable for 400 dpi/A3 high-speed digital copiers, OCRs and
high-end business facsimiles.
FEATURES
• Valid photocell
: 5000 pixels
• Photocell’s pitch
: 7 µm
• High sensitivity
: 9.0 V/lx·s TYP. (Light source: Daylight color fluorescent lamp)
• Low image lag
: 1 % MAX.
• Peak response wavelength : 550 nm (green)
• Resolution
: 16 dot/mm (400 dpi) A3 (297 × 420 mm) size (shorter side)
• Data rate
: 40 MHz MAX. (20 MHz/1 output)
• Output type
: 2 outputs out of phase (2 outputs in phase also supported)
• Power supply
: +12 V
• Drive clock level
: CMOS output under 5 V operation
• On-chip circuit
: Automatic φR level adjuster
• Pin assign
: Functional compatible with the µPD35H71A
ORDERING INFORMATION
Part Number
µPD3739D
Package
CCD linear image sensor 22-pin ceramic DIP (CERDIP) (400 mil)
The information in this document is subject to change without notice.
Document No. S12744EJ1V0DS00 (1st edition)
Date Published September 1997 N
Printed in Japan
© 1997

1 page




UPD3739D pdf
µPD3739
ABSOLUTE MAXIMUM RATINGS (TA = +25 ˚C)
Parameter
Output drain voltage
Shift register clock voltage
Reset gate clock voltage
Transfer gate clock voltage
Operating ambient temperature
Storage temperature
Symbol
VOD
Vφ1, Vφ2
VφR1, VφR2
VφTG
TA
Tstg
Ratings
–0.3 to +15
–0.3 to +15
–0.3 to +15
–0.3 to +15
–25 to +55
–40 to +100
Unit
V
V
V
V
˚C
˚C
Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
RECOMMENDED OPERATING CONDITIONS (TA = –25 to +55 ˚C)
Parameter
Output drain voltage
Shift register clock high level
Shift register clock low level
Reset gate clock high level
Reset gate clock low level
Capacitance of reset gate clock pin external capacitor
Transfer gate clock high level
Transfer gate clock low level
Data rate
Symbol
Conditions
VOD
Vφ1H, Vφ2H
Vφ1L, Vφ2L
VφR1H, VφR2H Note
VφR1L, VφR2L Note
CEXTφR
Non-polar type
VφTGH
VφTGL
2fφR1, 2fφR2
MIN.
11.4
4.5
–0.3
4.5
–0.3
800
4.5
–0.3
0.5
TYP.
12.0
5.0
0
5.0
0
1000
5.0
0
2
MAX.
12.6
5.5
+0.5
5.5
+0.5
1200
5.5
+0.5
40
Unit
V
V
V
V
V
pF
V
V
MHz
Note Input the reset gate clocks 1 and 2 (φR1, φR2) to pins 5 and 18, respectively, via an input resistor and a capacitor.
Use of a capacitor is indispensable. Refer to APPLICATION CIRCUIT EXAMPLE for the connection method.
The reset gate clock high level and low level at the IC pins (after passing through the external capacitor) varies
according to the IC, due to the on-chip automatic φR level adjuster. The recommended operating conditions
of reset gate clocks 1, 2 (φR1, φR2) in the table above are for signals applied to the external capacitor.
Remark φ1 in the above tables represents φ11, φ12 and φ1L2. φ2 represents φ21, φ22 and φ2L1.
5

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UPD3739D arduino
TIMING CHART 4 (In phase operation)
φ TG
φ 11
φ 21
φ 2L1
φ R1
VOUT1
φ 12
φ 22
φ 1L2
φ R2
VOUT2
Note
Optical black
(22 pixels)
Note Input the φR1 and φR2 pulses continuously during this period, too.
Invalid photocell
(2 pixels)
Valid photocell
(5000 pixels)
Invalid photocell
(2 pixels)

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