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PDF UPD30500RJ-200 Data sheet ( Hoja de datos )

Número de pieza UPD30500RJ-200
Descripción VR5000TM/ VR5000ATM/ VR5000BTM 64-BIT MICROPROCESSOR
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD30500, 30500A, 30500B
VR5000TM, VR5000ATM, VR5000BTM
64-BIT MICROPROCESSOR
DESCRIPTION
The µPD30500 (VR5000), µPD30500A (VR5000A), and µPD30500BNote (VR5000B) are a high-performance, 64-
bit RISC (Reduced Instruction Set Computer) type microprocessors employing the RISC architecture developed by
MIPSTM Technologies Inc.
The instructions of the VR5000, VR5000A, and VR5000B are compatible with those of the VR3000TM Series and
VR4000TM Series and higher, and completely compatible with those of the VR10000TM. Therefore, present
applications can be used as they are.
Note Under development
Detailed functions are described in the following manual. Be sure to read the manual when
designing your system.
• VR5000, VR5000A, VR5000B User’s Manual (U11761E)
FEATURES
• Employs 64-bit MIPS-based RISC architecture
• High-speed processing
• 2-way super scalar 5-stage pipeline
• 5.5 SPECint95, 5.5 SPECfp95, 278 MIPS (µPD30500)
6.6 SPECint95, 6.6 SPECfp95, 353 MIPS (µPD30500A)
8 SPECint95, 8 SPECfp95, 423 MIPS (µPD30500B)
• High-speed translation buffer mechanism (TLB) (48 entries)
• Address space Physical: 36 bits, Virtual: 40 bits
• Floating-point unit (FPU)
• Sum-of-products operation instruction supported
• Primary cache memory (instruction/data: 32 Kbytes each)
• Secondary cache controller
• Maximum operating frequency Internal: 200 MHz (µPD30500), 250 MHz (µPD30500A), 300 MHz (µPD30500B)
External: 100 MHz
• Selectable external/internal multiple rate from twice to eight times
• Instruction set compatible with VR3000 and VR4000 Series and higher (conforms to MIPS I, II, III, and IV)
• Supply voltage: 3.3 V ±5% (µPD30500)
Core: 2.5 V ±5%, I/O: 3.3 V ±5% (µPD30500A)
Core: 1.8 V ±0.1 V, I/O: 3.3 V ±5% (µPD30500B)
Unless otherwise specified, the VR5000 (µPD30500) is treated as the representative model throughout this
document.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U12031EJ4V0DS00 (4th edition)
Date Published May 2000 N CP(K)
Printed in Japan
The mark shows major revised points.
© 1997,1999
© MIPS Technologies Inc. 1997

1 page




UPD30500RJ-200 pdf
• 272-pin plastic BGA (C/D advanced type) (29 × 29)
µPD30500S2-150
µPD30500S2-180
µPD30500S2-200
µPD30500AS2-250
µPD30500BS2-300Note
µPD30500, 30500A, 30500B
Bottom View
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AA Y W V U T R P N M L K J H G F E D C B A
Top View
A B C D E F G H J K L M N P R T U V W Y AA
Note Under development
Data Sheet U12031EJ4V0DS00
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UPD30500RJ-200 arduino
µPD30500, 30500A, 30500B
1. PIN FUNCTIONS
Pin Name
SysAD (0:63)
SysADC (0:7)
SysCmd (0:8)
SysCmdP
ValidIn
ValidOut
ExtRqst
Release
WrRdy
RdRdy
ScCLR
ScCWE (0:1)
ScDCE (0:1)
ScDOE
ScLine (0:15)
ScMatch
ScTCE
ScTDE
ScTOE
ScWord (0:1)
ScValid
I/O Function
I/O System address/data bus.
64-bit bus for communication between processor, secondary cache and external agent.
I/O System address/data check bus.
8-bit bus including check bits for the SysAD bus.
I/O System command/data ID bus.
9-bit bus for communication of commands and data identifiers between processor
and external agent.
I/O System command/data ID bus parity.
1-bit even number parity bit for the SysCmd bus.
Input
Valid in.
Signal indicating that external agent has transmitted valid address or data onto
SysAD bus and valid command or data identifier onto SysCmd bus.
Output
Valid out.
Signal indicating that processor has transmitted valid address or data onto SysAD
bus and valid command or data identifier onto SysCmd bus.
Input
External request.
Signal used by external agent to request for its use by system interface.
Output Interface release.
Signal indicating that the processor has released the system interface to the slave state.
Output Write ready.
Signal indicating that the external agent can accept a processor write request.
Input
Read ready.
Signal indicating that external agent can accept a processor read request.
Output Secondary cache block clear.
Clears all the valid bits of the tag RAM.
Output Secondary cache write enable.
Write enable signal for the secondary cache RAM.
Output Data RAM chip select.
Chip select signal for secondary cache RAM.
Input
Data RAM output enable.
Data output enable signal from the external agent.
Output Secondary cache line index.
Cache line index output of the secondary cache.
Input
Secondary cache tag match.
Tag match signal from secondary cache tag RAM.
Output Secondary cache tag RAM chip select.
Chip select signal of the secondary cache tag RAM.
Output Secondary cache tag RAM data enable.
Data enable signal from the secondary cache tag RAM.
Output Secondary cache tag RAM output enable.
Output enable signal from the secondary cache tag RAM.
I/O Secondary cache word index.
Signal indicating that the double word of the secondary cache index is correct.
I/O Secondary cache valid.
Signal indicating that the data of the secondary cache is valid.
Data Sheet U12031EJ4V0DS00
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