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PDF UPD17P709GC-3B9 Data sheet ( Hoja de datos )

Número de pieza UPD17P709GC-3B9
Descripción 4-BIT SINGLE-CHIP MICROCONTROLLER WITH BUILT-IN HARDWARE DEDICATED TO DIGITAL TUNING SYSTEMS
Fabricantes NEC 
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD17P709
4-BIT SINGLE-CHIP MICROCONTROLLER WITH
BUILT-IN HARDWARE DEDICATED TO DIGITAL TUNING SYSTEMS
The µPD17P709 is produced by replacing the built-in masked ROM of the µPD17704Note, µPD17705Note,
µPD17707, µPD17708, and µPD17709 with a one-time PROM.
The µPD17P709 allows programs to be written once, so that the µPD17P709 is suitable for preproduction in
µPD17704, µPD17705, µPD17707, µPD17708, or µPD17709 system development or low-volume production.
When reading this document, also refer to the publications on the µPD17704, µPD17705, µPD17707,
µPD17708, or µPD17709.
Note Under development
The electrical characteristics (including power supply currents) and PLL analog characteristics of
the µPD17P709 differ from those of the µPD17704, µPD17705, µPD17707, µPD17708, and µPD17709. In
high-volume application set production, carefully check those differences.
FEATURES
Compatible with the µPD17704, µPD17705, µPD17707, µPD17708, and µPD17709
Built-in one-time PROM : 32K bytes (16384 × 16 bits)
Supply voltage
: VDD = 5 V ±10%
ORDERING INFORMATION
Part number
µPD17P709GC-3B9
Package
80-pin plastic QFP (14 × 14 mm, 0.65-mm pitch)
The information in this document is subject to change without notice.
Document No. U10142EJ2V0DS00 (2nd edition)
Date Published November 1996 P
Printed in Japan
The mark shows major revised points.
© 1995

1 page




UPD17P709GC-3B9 pdf
(2) PROM programming mode
µPD17P709
(L)
(OPEN)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1 60
2 59
3 58
4 57
5 56
6 55
7 54
8 53
9 52
10 51
11 50
12 49
13 48
14 47
15 46
16 45
17 44
18 43
19 42
20 41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
(L)
D0
D1
D2
D3
D4
D5
D6
D7
(L)
Note Connect to the same potential as VDD.
Caution The parentheses above indicate the handling of the pins not used in PROM programming mode.
L : Connect each pin to GND through a resistor (470 ohms).
H : Connect each pin to VDD through a resistor (470 ohms).
OPEN : Leave each pin open.
5

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UPD17P709GC-3B9 arduino
µPD17P709
Pin No.
30
79
Symbol
VDD1
VDD0
31 VCOH
32 VCOL
Function
Power supply. Apply the same voltage to the VDD1 and VDD0 pins.
• When the CPU and peripheral functions are operating: 4.5 to 5.5 V
• When only the CPU is operating: 3.5 to 5.5 V
• When the clock is stopped: 2.2 to 5.5 V
Input for PLL local oscillation (VCO) frequency
VCOH
• Active when VHF mode is selected by software. Otherwise, pulled
down.
VCOL
• Active when HF or MW mode is selected by software. Otherwise,
pulled down.
Output format
34 EO0
35 EO1
Inputs to these pins are to be AC-amplified. Cut, therefore, the DC
components in the input signals by using capacitors.
Output from the charge pump of the PLL frequency synthesizer. The
result of phase comparison between the divided local oscillation fre-
quency and reference frequency is output.
CMOS tristate
36 TEST
Power-on reset
When reset
WDT&SP reset
CE reset
When the clock
is stopped
High-impedance High-impedance High-impedance High-impedance
output
output
output
output
Test input pin.
Be sure to connect it to GND.
37 P1D3
38 P1D2
Output for port 1D and BEEP
P1D3-P1D0
39 P1D1/BEEP1
• 4-bit I/O port
40 P1D0/BEEP0
• Input/output can be specified bit by bit.
BEEP1, BEEP0
• BEEP output
CMOS push-pull
Power-on reset
Input
(P1D3-P1D0)
When reset
WDT&SP reset
CE reset
Input
(P1D3-P1D0)
Held
(P1D3-P1D0)
When the clock
is stopped
Held
(P1D3-P1D0)
43 P2B3
to to
46 P2B0
4-bit I/O port.
Input/output can be specified bit by bit.
Power-on reset
Input
When reset
WDT&SP reset
Input
CE reset
Held
When the clock
is stopped
Held
CMOS push-pull
47 P3C3
to to
50 P3C0
4-bit I/O port.
Input/output can be specified in 4-bit units.
Power-on reset
Input
When reset
WDT&SP reset
Input
CE reset
Held
When the clock
is stopped
Held
CMOS push-pull
11

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