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PDF UPD178P018AKK Data sheet ( Hoja de datos )

Número de pieza UPD178P018AKK
Descripción 8-BIT SINGLE-CHIP MICROCONTROLLER
Fabricantes NEC 
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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD178P018A
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD178P018ANote is a device in which the internal mask ROM of the µPD178018A is replaced with a one-
time PROM or EPROM.
Because this device can be programmed by users, it is ideally suited for system evaluation, small-lot and multiple-
device production, and early development and time-to-market.
The µPD178P018A is a PROM version corresponding to the µPD178004A, 178006A, and 178016A.
Note Under development
Caution The µPD178P018AKK-T does not maintain planned reliability when used in your system’s mass-
produced products. Please use only experimentally or for evaluation purposes during trial manufacture.
For more information on functions, refer to the following User’s Manuals. Be sure to read them when
designing.
µPD178018A Subseries User’s Manual: To be prepared
78K/0 Series User’s Manual Instruction: U12326E
FEATURES
• Pin-compatible with mask ROM version (except for VPP pin)
• Internal PROM: 60 Kbytes
µPD178P018AGC : One-time programmable (ideally suited for small-lot production)
µPD178P018AKK-T : Reprogrammable (ideally suited for system evaluation)
• Internal high-speed RAM: 1 024 bytes
• Internal expansion RAM: 2 048 bytes
• Buffer RAM: 32 bytes
• Can be operated in the same power supply voltage as the mask ROM version
(During PLL operation: VDD = 4.5 to 5.5 V)
The electrical specifications (power supply current, etc.) and PLL analog specifications of the µPD178P018A differ
from that of mask ROM versions. So, these differences should be considered and verified before application sets
are mass-produced.
In this document, the term PROM is used in parts common to one-time PROM versions and EPROM versions.
The information in this document is subject to change without notice.
Document No. U12642EJ1V0DS00 (1st Edition)
Date Published July 1997 N
Printed in Japan
©
1997

1 page




UPD178P018AKK pdf
PIN CONFIGURATIONS (TOP VIEW)
(1) Normal operating mode
80-PIN PLASTIC QFP (14 × 14 mm, 0.65-mm pitch)
µPD178P018AGC-3B9 Note
80-PIN CERAMIC WQFN (14 × 14 mm, 0.65-mm pitch)
µPD178P018AKK-T Note
µPD178P018A
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P20/SI1
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P132/PWM0
P133/PWM1
P134/PWM2
P40
P41
P42
180 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 6160
2 59
3 58
4 57
5 56
6 55
7 54
8 53
9 52
10 51
11 50
12 49
13 48
14 47
15 46
16 45
17 44
18 43
19 42
2021 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 4041
P37
P36/BEEP
P35
P34/TI2
P33/TI1
P32
P31
P30
P67
P66
P65
P64
P63
P62
P61
P60
P57
P56
P55
P54
Note Under development
Cautions 1. Connect the VPP pin to GND directly.
2. Connect the VDDPORT and VDDPLL pins to VDD.
3. Connect the GNDPORT and GNDPLL pins to GND.
4. Connect each of the REGOSC and REGCPU pins to GND via a 0.1-µF capacitor.
5

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UPD178P018AKK arduino
µPD178P018A
(2) Non-port pins (1 of 2)
Pin Name I/O
INTP0 to
INTP6
Input
SI0 Input
SI1
SO0
Output
SO1
SB0 I/O
SB1
SDA0
SDA1
SCK0
I/O
SCK1
SCL
STB Output
BUSY
Input
TI1 Input
TI2
BEEP
Output
ANI0 to ANI5 Input
PWM0 to
PWM2
Output
EO0, EO1 Output
VCOL
Input
VCOH
Input
AMIFC
Input
FMIFC
Input
RESET
Input
X1 Input
X2 —
REGOSC
REGCPU
VDD
GND
VDDPORT
GNDPORT
VDDPLL Note
GNDPLL Note
Function
External maskable interrupt inputs with specifiable valid edges (rising
edge, falling edge, both rising and falling edges).
Serial interface serial data input
Serial interface serial data output
Serial interface serial data input/output
Serial interface serial clock input/output
Serial interface automatic transmit/receive strobe output
Serial interface automatic transmit busy input
External count clock input to 8-bit timer (TM1)
External count clock input to 8-bit timer (TM2)
Buzzer output
A/D converter analog input
PWM output
After Reset Alternate Function
Input
P00 to P06
Input
Input
Input
Input
Input
Input
Input
Input
Input
P25/SB0/SDA0
P20
P26/SB1/SDA1
P21
P25/SI0/SDA0
P26/SO0/SDA1
P25/SI0/SB0
P26/SO0/SB1
P27/SCL
P22
P27/SCK0
P23
P24
P33
P34
P36
P10 to P15
P132 to P134
Error out output from charge pump of the PLL frequency synthesizer
Inputs PLL local band oscillation frequency (In HF, MF mode).
Inputs PLL local band oscillation frequency (In VHF mode).
Inputs AM intermediate frequency counter.
Inputs FM intermediate frequency counter.
System reset input
Crystal resonator connection for system clock oscillation
Regulator for oscillator. Connected to GND via a 0.1-µF capacitor.
Regulator for CPU power supply. Connected to GND via a 0.1-µF capacitor.
Positive power supply
Ground
Positive power supply for port block
Ground for port block
Positive power supply for PLL
Ground for PLL
Note Connect a capacitor of approximately 1 000 pF between VDDPLL pin and GNDPLL pin.
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