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PDF UPD178018AGC Data sheet ( Hoja de datos )
| Número de pieza | UPD178018AGC | |
| Descripción | 8-BIT SINGLE-CHIP MICROCONTROLLERS | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD178004A, 178006A, 178016A, 178018A
8-BIT SINGLE-CHIP MICROCONTROLLERS
The µPD178004A, 178006A, 178016A and 178018A are 8-bit single-chip CMOS microcontrollers that incorporate
hardware for digital tuning systems.
The CPU uses the 78K/0 architecture, which makes it easy to implement high-speed access to internal memory
and control of peripheral hardware. Also, the instructions used are the high-speed 78K/0 instructions, suitable for
system control.
The rich assortment of peripheral hardware includes an input/output port, 8-bit timer, A/D converter, serial interface,
power-ON clear circuits, as well as a pre-scaler for digital tuning, a PLL frequency synthesizer and a frequency counter.
The µPD178P018A, one-time PROM or EPROM versions which can be operated in the same supply voltage range
as for the mask ROM versions, and various development tools, are also available.
For more information on functions, refer to the following User’s Manuals. Be sure to read them when
designing.
µPD178018A Subseries User’s Manual: to be prepared
78K/0 Series User’s Manual Instruction: U12326E
FEATURES
• Internal high-capacity ROM and RAM
Items
Product Name
µPD178004A
µPD178006A
µPD178016A
µPD178018A
Program Memory
ROM
Internal High-Speed RAM
32 Kbytes
1 024 bytes
48 Kbytes
60 Kbytes
Data Memory
Buffer RAM
32 bytes
Internal Expanded RAM
Not provided
2 048 bytes
• Instruction Cycle: 0.44 µs (4.5-MHz crystal oscillator used)
• Large array of on-chip peripheral hardware
General-purpose input/output port, A/D converter, serial interface, timer, frequency counter, power-ON clear
circuits.
• On-chip hardware for a PLL frequency synthesizer.
Dual modulus pre-scaler, programmable divider, phase comparator, charge pump.
• Vector interrupt sources: 17
• Supply Voltage: VDD = 4.5 to 5.5 V (during PLL operation)
VDD = 3.5 to 5.5 V (during CPU operation, when the system clock is fX/2 or lower)
VDD = 4.5 to 5.5 V (during CPU operation, when the system clock is fX)
The information in this document is subject to change without notice.
Document No. U12641EJ1V0DS00 (1st Edition)
Date Published July 1997 N
Printed in Japan
©
1997
1 page  
µPD178004A, 178006A, 178016A, 178018A
TABLE OF CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ................................................................................................ 6
2. BLOCK DIAGRAM ........................................................................................................................... 8
3. PIN FUNCTION LIST ........................................................................................................................ 9
3.1 PORT PINS ................................................................................................................................ 9
3.2 PINS OTHER THAN PORT PINS ............................................................................................ 10
3.3 INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS ..... 11
4. MEMORY SPACE .......................................................................................................................... 14
5. PERIPHERAL HARDWARE FUNCTION FEATURES .................................................................. 15
5.1 PORTS ..................................................................................................................................... 15
5.2 CLOCK GENERATOR ............................................................................................................ 16
5.3 TIMER ...................................................................................................................................... 16
5.4 BUZZER OUTPUT CONTROL CIRCUIT ................................................................................ 18
5.5 A/D CONVERTER ................................................................................................................... 19
5.6 SERIAL INTERFACES ............................................................................................................ 19
5.7 PLL FREQUENCY SYNTHESIZER ........................................................................................ 21
5.8 FREQUENCY COUNTER ........................................................................................................ 22
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS .................................................................... 23
6.1 INTERRUPT FUNCTIONS ...................................................................................................... 23
6.2 TEST FUNCTION .................................................................................................................... 26
7. STANDBY FUNCTION ................................................................................................................... 27
8. RESET FUNCTION ........................................................................................................................ 27
9. INSTRUCTION SET ....................................................................................................................... 28
10. ELECTRICAL SPECIFICATIONS .................................................................................................. 30
11. PACKAGE DRAWINGS ................................................................................................................. 46
12. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 47
APPENDIX A. DIFFERENCES BETWEEN µPD178018A AND µPD178018 SUBSERIES ............... 48
APPENDIX B. DEVELOPMENT TOOLS ............................................................................................ 49
APPENDIX C. RELATED DOCUMENTS ........................................................................................... 51
5
5 Page 
µPD178004A, 178006A, 178016A, 178018A
3.3 INPUT/OUTPUT CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins.
Refer to Figure 3-1 for the configuration of the input/output circuit of each type.
Table 3-1. I/O Circuit Type of Each Circuit
Pin Name
P00/INTP0
P01/INTP1 to P06/INTP6
P10/ANI0 to P15/ANI5
P20/SI1
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P30 to P32
P33/TI1, P34/TI2
P35
P36/BEEP
P37
P40 to P47
P50 to P57
P60 to P63
P64 to P67
P120 to P125
P132/PWM0 to P134/PWM2
EO0
EO1
VCOL, VCOH
AMIFC, FMIFC
IC
I/O Circuit Type
2
8
11-A
8
5
8
5
8
10
I/O
Input
I/O
Recommended Connections of Unused Pins
Connected to GND or GNDPORT
Set in general-purpose input port mode by software and
individually connected to VDD, VDDPORT, GND, or GNDPORT
via resistor.
5
8
5
5-G
5
13-D
5
19
DTS-EO1
DTS-EO3 Note
DTS-AMP
Output Set to low-level output by software and open
Open
Input Set to disabled status by software and open
— — Connected to GND or GNDPORT directly
Note For the µPD178004A and 178006A, the I/O circuit type is DTS-EO1.
11
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