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PDF UPD17705 Data sheet ( Hoja de datos )

Número de pieza UPD17705
Descripción 4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED HARDWARE FOR DIGITAL TUNING SYSTEM
Fabricantes NEC 
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD17704, 17705, 17707, 17708, 17709
4-BIT SINGLE-CHIP MICROCONTROLLERS WITH DEDICATED
HARDWARE FOR DIGITAL TUNING SYSTEM
The µPD17704, 17705, 17707, 17708, and 17709 are 4-bit single-chip CMOS microcontrollers containing
hardware for digital tuning systems.
Provided with a wealth of hardware, these microcontrollers are available in many variations of ROM and RAM
capacities to support various applications.
Therefore, a high-performance, multi-function digital tuning system can be configured with only one chip.
In addition, a one-time PROM model, µPD17P709, which can be written only once and therefore is ideal for
program evaluation and small-scale production of a µPD17704, 17705, 17707, 17708, or 17709 system, is also
available.
FEATURES
Program memory (ROM)
General Purpose data
memory (RAM)
µPD17704
µPD17705
µPD17707
16K bytes
24K bytes
(8192 × 16 bits) (12288 × 16 bits)
672 × 4 bits
1120 × 4 bits
µPD17708
µPD17709
32K bytes
(16384 × 16 bits)
1776 × 4 bits
• Instruction execution time
1.78 µs (with fX = 4.5-MHz crystal oscillator)
• PLL frequency synthesizer
Dual modulus prescaler (130 MHz MAX.),
programmable divider, phase comparator, charge
pump
• Abundant peripheral hardware units
General-purpose I/O ports, serial interfaces, A/D
converter, D/A converter (PWM output), BEEP
output, frequency counter
• Many interrupts
External
: 6 sources
Internal
: 6 sources
• Power-ON reset, CE reset, and power failure
detection circuit
• Supply voltage: VDD = 5 V ± 10 %
Unless otherwise specified, the µPD17709 is treated as the representative model in this document.
The information in this document is subject to change without notice.
Document No. U11624EJ2V0DS00 (2nd edition)
Date Published December 1996 N
Printed in Japan
The mark shows major revised points.
©
1996

1 page




UPD17705 pdf
µPD17704, 17705, 17707, 17708, 17709
PIN NAME
AD0-AD5
: A/D converter input
AMIFC
: AM frequency counter input
BEEP0, BEEP1 : BEEP output
CE : Chip enable
EO0, EO1
: Error-out output
FCG0, FGC1 : Frequency counter gate input
FMIFC
: FM frequency counter input
GND0-GND2 : Ground 0 to 2
INT0-INT4
: External interrupt input
PWM0-PWM2 : D/A converter output
P0A0-P0A3 : Port 0A
P0B0-P0B3 : Port 0B
P0C0-P0C3 : Port 0C
P0D0-P0D3 : Port 0D
P1A0-P1A3 : Port 1A
P1B0-P1B3 : Port 1B
P1C0-P1C3 : Port 1C
P1D0-P1D3 : Port 1D
P2A0-P2A2 : Port 2A
P2B0-P2B3 : Port 2B
P2C0-P2C3
P2D0-P2D2
P3A0-P3A3
P3B0-P3B3
P3C0-P3C3
P3D0-P3D3
REG
RESET
SCK0, SCK1
SCL
SDA
SI0, SI1
SO0, SO1
TEST
TM0G
VCOH
VCOL
VDD0, VDD1
XIN, XOUT
: Port 2C
: Port 2D
: Port 3A
: Port 3B
: Port 3C
: Port 3D
: CPU regulator
: Reset input
: 3-wire serial clock I/O
: 2-wire serial clock I/O
: 2-wire serial data I/O
: 3-wire serial data input
: 3-wire serial data output
: Test input
: Timer 0 gate input
: Local oscillation high input
: Local oscillation low input
: Power supply
: Main clock oscillation
5

5 Page





UPD17705 arduino
µPD17704, 17705, 17707, 17708, 17709
1. PIN FUNCTIONS
1.1 Pin Function List
Pin No. Symbol
1 INT2
41 INT1
42 INT0
2 P1A3/INT4
3 P1A2/INT3
4 P1A1
5 P1A0/TM0G
6 P3A3
||
9 P3A0
10 P3B3
||
13 P3B0
14 P2A2
15 P2A1/FCG1
16 P2A0/FCG0
Function
Edge-detectable vectored interrupt input pins. Rising or falling edge can be
specified.
Output Form
Port 1A multiplexed with external interrupt request signal input and event
signal input pins.
• P1A3 through P1A0
• 4-bit input port
• INT4, INT3
• Edge-detectable vectored interrupt
• TM0G
• Input for gate of 8-bit timer 0
At reset
With clock stopped
Power-ON reset WDT&SP reset
CE reset
Input
Input
Retained
(P1A3 through P1A0) (P1A3 through P1A0)
Retained
4-bit I/O port.
Can be set in input or output mode in 4-bit units.
CMOS
push-pull
At reset
With clock stopped
Power-ON reset WDT&SP reset
CE reset
Input
Input
Retained
Retained
4-bit I/O port.
Can be set in input or output mode in 4-bit units.
CMOS
push-pull
At reset
With clock stopped
Power-ON reset WDT&SP reset
CE reset
Input
Input
Retained
Retained
Port 2A multiplexed with external gate counter input pins.
• P2A2 through P2A0
• 3-bit I/O port
• Can be set in input or output mode in 1-bit units.
• FCG1, FCG0
• Input for external gate counter
CMOS
push-pull
At reset
With clock stopped
Power-ON reset WDT&SP reset
CE reset
Input
Input
Retained
Retained
(P2A2 through P2A0) (P2A2 through P2A0) (P2A2 through P2A0) (P2A2 through P2A0)
11

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