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PDF UPD17068 Data sheet ( Hoja de datos )

Número de pieza UPD17068
Descripción 4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING IMAGE DISPLAY CONTROLLER AND PLL FREQUENCY SYNTHESIZER FOR DIGITAL TUNING SYSTEMS
Fabricantes NEC 
Logotipo NEC Logotipo



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No Preview Available ! UPD17068 Hoja de datos, Descripción, Manual

DATA SHEET
MOS INTEGRATED CIRCUIT
µPD17068
4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING
IMAGE DISPLAY CONTROLLER AND PLL FREQUENCY
SYNTHESIZER FOR DIGITAL TUNING SYSTEMS
The µPD17068 is a 4-bit single-chip microcontroller for digital tuning systems. It contains an image display
controller (IDC) that supports many types of display, and a PLL synthesizer.
The CPU of the µPD17068 is capable of 4-bit parallel addition, logical operations, bit tests, setting/resetting
of a carry flag, and supports a powerful interrupt function and timer function.
The image display controller for on-screen display is user-programmable, allowing a range of displays to
be programmed.
The peripheral hardware includes a full complement of I/O ports, controlled with powerful I/O instructions,
as well as a serial interface, a 6-bit A/D converter, and an 8-bit D/A converter (PWM output).
FEATURES
• Program memory (ROM) : 24K bytes (12032 × 16 bits)
• Character ROM (CROM) : 4086 × 24 bits (255 characters)
• Data memory (RAM)
: 1007 × 4 bits
• Video RAM (VRAM)
: 672 × 4 bits (can be used for data memory)
• Address stack
: 12 levels
• Interrupt stack
: 2 levels
• Instruction execution time : 2 µs (when an 8 MHz crystal is used)
• PLL frequency synthesizer
• 8-bit serial interface
(2 channels: One for two-wire or three-wire mode, compatible with I2C bus, and one for three-wire mode only)
• D/A converter: 8 bits × 9 lines (PWM output)
• A/D converter: 6 bits × 8 lines
• Horizontal synchronizing signal counter
• Commercial power supply frequency counter
• Power-failure detection circuit and power-on reset circuit
• Interrupt input for remote-controller signal (with noise canceler)
• User-programmable image display controller (IDC)
Displayed characters : Up to 192 per screen (more characters can be displayed when the use of the entire
screen is specified with a program)
Display mode
: 16 × 16 dots in 15 lines × 24 columns
14 × 16 dots in 17 lines × 24 columns
Character patterns : 255
Character format
: 16 × 16 dots or 14 × 16 dots
Colors
: 15
Character sizes
: 16 sizes for height (can be specified per line)
24 sizes for width (can be specified per character)
• Many I/O ports
I/O : 19 ports
Input only
: 4 ports
Output only
: 21 ports
• Operating supply voltage: 5 V ±10 %
• Low power dissipation by use of CMOS technology
The information in this document is subject to change without notice.
Document No. IC-3525
(O.D. No. IC-8999)
Date Published November 1994 P
Printed in Japan
© 1994

1 page




UPD17068 pdf
BLOCK DIAGRAM
VCO
PSC
EO
OSCIN
OSCOUT
HSYNC
VSYNC
RED
GREEN
BLUE
BLANK
I (POB2)
HSCNT (P0B3)
PLL
OSC
circuit
IDC
Hsync
counter
P0A0-P0A3
4
P0B0-P0B3
P0C0-P0C3
4
4
P0D0-P0D3
4
P1A0-P1A3
P1B0-P1B3
4
4
P1C0-P1C3
P1D0-P1D3
4
4
P2A0
P2B0-P2B3
P2C0-P2C3
4
4
P2D0-P2D3
XIN
XOUT
VDD
CE
RLSSTP/PIB2
GND0, GND1
3
Port
Main
OSC
Reset
RAM
1007 × 4 bits
VRAM
(672 × 4 bits)
System registers
RF
ALU
Instruction decoder
ROM
12032 × 16 bits
CROM
4086 × 24 bits
Program counter
Stack
12 × 14 bits
CPU
Peripheral
µPD17068
A/D
Converter
D/A
converter
OSC
Watch
timer
Timer 0
Timer 1
Basic
timer 0
Basic
timer 1
Basic
timer 2
Serial
interface 0
Serial
interface 1
Interrupt
ADC0
ADC1 (P0D0/XTOUT)
ADC2 (P0D1/XTIN)
ADC3 (P0D2)
ADC4 (P0D3)
ADC5 (P1C0)
|
ADC7 (P1C2)
PWM0 (P2C0)
|
PWM3 (P2C3)
PWM4 (P2B0)
|
PWM7 (P2B3)
PWM8 (P2A0)
XTIN (P0D1/ADC2)
XTOUT (P0D0/ADC1)
CKOUT (P1B1)
TMIN (P1B3)
SDA (P0A0)
SCL (P0A1)
SCK0 (P0A2)
SO0 (P0A3)
SI0 (P0B0)
SCK1 (P2D0)
SO1 (P2D1)
SI1 (P2D2)
INTNC
INT0
5

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UPD17068 arduino
µPD17068
11. INTERRUPT ................................................................................................................................. 102
11.1 OUTLINE OF THE INTERRUPT BLOCK ........................................................................................ 102
11.2 INTERRUPT CONTROL BLOCKS ................................................................................................... 104
11.2.1 Formats and Functions of Interrupt Request Flags (IRQ×××) .................................. 104
11.2.2 Interrupt Enable Flags (IP×××) ...................................................................................... 110
11.2.3 Vector Address Generator (VAG) ................................................................................ 112
11.3 INTERRUPT STACK REGISTER ..................................................................................................... 113
11.3.1 Format and Functions of the Interrupt Stack Register ............................................ 113
11.3.2 Interrupt Stack Operation ............................................................................................. 113
11.4 STACK POINTER, ADDRESS STACK REGISTER, AND PROGRAM COUNTER ....................... 114
11.5 INTERRUPT ENABLE FLIP-FLOP (INTE) ....................................................................................... 114
11.6 ACCEPTING INTERRUPTS ............................................................................................................. 115
11.6.1 Operation for Accepting Interrupts and Priorities .................................................... 115
11.6.2 Timing Charts for Accepting Interrupts ...................................................................... 116
11.7 OPERATION AFTER AN INTERRUPT IS ACCEPTED .................................................................. 119
11.8 RETURN FROM THE INTERRUPT HANDLING ROUTINE........................................................... 119
11.9 EXTERNAL INTERRUPTS (INT0 PIN, INTNC PIN, VSYNC PIN, HSYNC PIN) ................................... 120
11.9.1 Outline of External Interrupts ...................................................................................... 120
11.9.2 Edge Detection Blocks ................................................................................................... 121
11.9.3 Interrupt Control Block ................................................................................................. 122
11.9.4 Input Pin for Remote Control (INTNC) .......................................................................... 123
11.10 INTERNAL INTERRUPTS ............................................................................................................... 123
11.10.1 Timer 0 Interrupt ............................................................................................................ 124
11.10.2 Timer 1 Interrupt ............................................................................................................ 124
11.10.3 Basic Timer 2 Interrupt ................................................................................................. 124
11.10.4 VRAM Pointer Interrupt ................................................................................................ 124
11.10.5 Serial Interface 0 Interrupt ........................................................................................... 124
11.10.6 Serial Interface 1 Interrupt ........................................................................................... 124
11.10.7 Interrupts by Interrupt Group 0 and Interrupt Group Selection Register ............. 125
12. TIMERS ........................................................................................................................................ 126
12.1 OVERVIEW ...................................................................................................................................... 126
12.2 BASIC TIMER 0 ............................................................................................................................... 128
12.2.1 Overview of Basic Timer 0 ............................................................................................ 128
12.2.2 Clock Selection Block .................................................................................................... 128
12.2.3 Flip-Flop and BTM0CY Flag .......................................................................................... 129
12.2.4 Example of Using Basic Timer 0 .................................................................................. 130
12.2.5 Time Interval Error in Basic Timer 0 ........................................................................... 131
12.2.6 Cautions for Using Basic Timer 0 ................................................................................ 134
12.3 BASIC TIMER 1 ............................................................................................................................... 140
12.3.1 Overview of Basic Timer 1 ............................................................................................ 140
12.3.2 Clock Selection Block .................................................................................................... 141
12.3.3 Flip-Flop and BTM1CY Flag .......................................................................................... 142
12.3.4 Time Interval Error in Basic Timer 1 ........................................................................... 142
12.4 BASIC TIMER 2 ............................................................................................................................... 143
12.4.1 Overview of Basic Timer 2 ............................................................................................ 143
12.4.2 Clock Selection Block .................................................................................................... 144
12.4.3 Example of Using Basic Timer 2 .................................................................................. 145
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