PDF UPD17062 Data sheet ( Hoja de datos )

Número de pieza	UPD17062
Descripción	4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING PLL FREQUENCY SYNTHESIZER AND IMAGE DISPLAY CONTROLLER
Fabricantes	NEC
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No Preview Available ! DATA SHEET MOS INTEGRATED CIRCUIT µPD17062 4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING PLL FREQUENCY SYNTHESIZER AND IMAGE DISPLAY CONTROLLER The µPD17062 is a 4-bit CMOS microcontroller for digital tuning systems. The single-chip device incorporates an image display controller enabling a range of different displays, together with a PLL frequency synthesizer. The CPU has six main functions: 4-bit parallel addition, logic operation, multiple bit test, carry-flag set/ reset, powerful interrupt, and a timer. The device contains a user-programmable image display controller (IDC) for on-screen displays. The different displays can be controlled with simple programs. The device also has a serial interface function, many input/output (I/O) ports controlled by powerful I/O instructions, and 6-bit pulse width modulation (PWM) output for a 4-bit A/D converter and D/A converter. FEATURES • 4-bit microcontroller for digital tuning system • Internal PLL frequency synthesizer: With prescaler µPB595 • 5 V ±10% • Low-power CMOS • Program memory (ROM): 8K bytes (16 bits × 3968 steps) • Data memory (RAM): 4 bits × 336 words • 6 stack levels • 35 easy-to-understand instruction sets • Support of decimal operations • Instruction execution time: 2 µs (with an 8-MHz crystal) • Internal D/A converter: 6 bits × 4 (PWM output) • Internal A/D converter: 4 bits × 6 • Internal horizontal synchronizing signal counter • Internal commercial power frequency counter • Internal power-failure detector and power-on reset circuit • Internal image display controller (IDC) (user-pro- grammable) Number of characters in display: Up to 99 on a single screen Display configuration: 14 rows × 19 columns Number of character types: 120 Character format: 10 × 15 dots (rimming possible) Number of colors: 8 Character size: Four sizes in each of the horizontal and vertical dimensions Internal 1H circuit for preventing vertical deflection • Internal 8-bit serial interface (One system with two channels: three-wire or two-wire) • Interrupt input for remote-controller signals (with noise canceler) • Many I/O ports Number of I/O ports : 15 Number of input ports : 4 Number of output ports: 8 Document No. IC-3560 (O.D. No. IC-8937) Date Published January 1995 P Printed in Japan The information in this document is subject to change without notice. © 1995 1 page BLOCK DIAGRAM VCO PSC EO HSYNC VSYNC RED GREEN BLUE BLANK P0A0/SDA P0A1/SCL P0A2/SCK P0A3/SO P0B0/SI P0B1 P0B2/TMIN P0B3/HSCNT PLL IDC Serial I/O P0A P0B Hsync Counter Timer Controller P0D0/ADC2 P0D1/ADC3 P0D2/ADC4 P0D3/ADC5 P1C3/ADC1 P1C2 P1C1 ADC0 P0D P1C A/D µPD17062 RF RAM 336 × 4 bits (Including VRAM) SYSREG ALU PWM P1A P1B ROM 3968 × 16 bits (Including CROM) Program Counter Stack 6 × 12 bits P0C Interrupt Controller Instruction Decoder CPU Peripheral OSC Reset PWM0 PWM1 PWM2 PWM3 P1A0 P1A1 P1A2 P1A3 P1B0 P1B1 P1B2 P1B3 P0C0 P0C1 P0C2 P0C3 INTNC XIN XOUT VDD CE GND 5 5 Page µPD17062 1. PINS 1.1 PIN FUNCTIONS Pin No. DIP QFP (GC) Symbol 1 58 \|\| 4 61 P0C3 \| P0C0 5 62 P0D3/ADC5 \|\| \| 8 1 P0D0/ADC2 92 \|\| 12 6 13 9 PWM3 \| PWM0 VDD VDD1 VDD0 14 11 15 13 VCO EO 16 15 17 16 GND GND2 GND1 GND0 PSC 18 17 CE 19 18 20 19 XOUT XIN Description 4-bit output port Input of port 0D and A/D converter • P0D3 to P0D0 4-bit input port containing a pull-down resis- tor. • ADC5 to ADC2 Input of a 4-bit A/D converter, which is a soft- ware-based successive-approximation type. The reference voltage is VDD. Output of a 6-bit D/A converter. The output type is PWM. Output is done at a frequency of 15.625 kHz. The pin can also be used as a one-bit output port. Supplies the power to the device. To enable all functions, 5 V ±10% is supplied. To operate only the CPU, 4 V is required. In the clock-stop state, the voltage can be reduced to 3.5 V. When the supply voltage increases from 0 V to 4 V, a power-on reset occurs and the program is started from address 0. Apply an identical voltage to all pins. Inputs the signal obtained by dividing the local oscillation output by the specialized prescaler. Outputs the PLL error signal. The signal is input through the external LPF to the local oscillation circuit. Grounds the device. Connect all pins to ground. Outputs the signal to switch the frequency divi- sion ratio of the specialized prescaler. Inputs the signal to select the device. To operate the PLL and IDC, set the input signal high. If the input signal is low, the device can be backed up with a low current drain by executing a stop instruction. When the input signal goes high, the device is reset and the program is started from address 0. Used to connect a crystal. An 8-MHz crystal is used. Output type CMOS push-pull — N-ch open drain — — CMOS tristate — CMOS push-pull — — — At power-on reset Undefined Input Undefined — Input Hi-z — Undefined Input — Input 11 11 Page

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