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PDF UPD16837 Data sheet ( Hoja de datos )
| Número de pieza | UPD16837 | |
| Descripción | MONOLITHIC QUAD H BRIDGE DRIVER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16837
MONOLITHIC QUAD H BRIDGE DRIVER
DESCRIPTION
The µPD16837 is a monolithic quad H bridge driver employing power MOS FETs in the output stage. The MOS FETs
in the output stage lower the saturation voltage and power consumption as compared with conventional drivers using bipolar
transistors.
In addition, a low-voltage malfunction prevention circuit is also provided that prevents the IC from malfunctioning when
the supply voltage drops. A 30-pin plastic shrink SOP package is adopted to help create compact and slim application sets.
In the output stage H bridge circuits, two low-ON resistance H bridge circuits for driving actuators, and another two
channels for driving sled motors and loading motors are provided, making the product ideal for applications in CD-ROM
and DVD.
FEATURES
• Four H bridge circuits employing power MOS FETs
• High-speed PWM drive: Operating frequency: 120 kHz MAX.
• Low-voltage malfunction prevention circuit: Operating voltage: 2.5 V (TYP.)
• 30-pin shrink SOP (300 mil)
ORDERING INFORMATION
Part Number
µPD16837GS
Package
30-pin plastic SSOP (300 mil)
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
Parameter
Symbol
Conditions
Control block supply voltage
VDD
Output block supply voltage
VM
Input voltage
H bridge drive currentNote 1
Power dissipationNote 2
VIN
IDR (pulse)
PT
PW ≤ 5 ms, Duty ≤ 30 %
Operating temperature range
TA
Peak junction temperature
TCH (MAX)
Storage temperature range
Tstg
Notes 1. When only one channel operates.
2. When mounted on a glass epoxy board (100 mm × 100 mm × 1 mm)
Rating
–0.5 to +7.0
–0.5 to +15
–0.5 to VDD + 0.5
±1.0
1.25
0 to 75
150
–55 to +150
Unit
V
V
V
A/phase
W
°C
°C
°C
The information in this document is subject to change without notice.
Document No. S12764EJ1V0DS00 (1st edition)
Date Published January 1998 N CP(K)
Printed in Japan
©
1998
1 page  
µPD16837
100
80
60
40
20
0
0
IDD vs. TA Characteristics
VDD = 6 V
20 40 60
Ambient temperature TA (°C)
1
0.8
0.6
0.4
0.2
0
0
ISa, ISb vs. TA Characteristics
ISb
ISa
VDD = 5 V
VM = 12 V
100 kHz
20 40 60
Ambient temperature TA (°C)
tTLH, tTHL vs. TA Characteristics (chs 1 and 4)
100
90
tTHL
80
tTLH
70
60 VDD = 5 V,
VM = 12 V
100 kHz, 10 Ω
50
0 20 40 60
Ambient temperature TA (°C)
VIH, VIL vs. TA Characteristics
2
VDD = 5 V
VM = 12 V
1.95
VIH
1.9
VIL
1.85
1.8
0
4
3
20 40 60
Ambient temperature TA (°C)
RON vs. TA Characteristics
RONa
2
RONb
1
VDD = 5 V
VM = 12 V
0
0 20 40 60
Ambient temperature TA (°C)
tTLH, tTHL vs. TA Characteristics (chs 2 and 3)
100
90
80 tTLH
70 tTHL
60 VDD = 5 V,
VM = 12 V
100 kHz, 20 Ω
50
0 20 40 60
Ambient temperature TA (°C)
5
5 Page 
µPD16837
The switching characteristics shown on the preceding pages are specified as follows (“output at one side” means
output B for H bridge output A, or output A for output B).
[Rise time]
Rise time when the output at one side is fixed to the low level (specified on current ON).
[Fall time]
Fall time when the output at one side is fixed to the high level (specified on current ON).
[Rising delay time]
Rising delay time when the output at one side is fixed to the low level (specified on current ON).
[Falling delay time]
Falling delay time when the output at one side is fixed to the high level (specified on current ON).
[Change in rising delay time]
Change (difference) in the rising delay time between when the output at one side is fixed to the low level and when
the output at the other side is fixed to the high level.
[Change in falling delay time]
Change (difference) in falling delay time between when the output at one side is fixed to the low level and when
the output at the other side is fixed to the high level.
[Rising delay time differential]
Difference in rising delay time between output A and output B.
[Falling delay time differential]
Difference in falling delay time between output A and output B.
Caution
Because this IC switches a high current at high speeds, surge may occur due to the VM and
GND wiring and inductance and degrade the performance of the IC.
On the PWB, keep the pattern width of the VM and GND lines as wide and short as possible,
and insert the bypass capacitors between VM and GND at a location as close to the IC as
possible.
Connect a low-inductance magnetic capacitor (4700 pF or more) and an electrolytic capacitor
of 10 µF or so, depending on the load current, in parallel.
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet UPD16837.PDF ] | |
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