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PDF UPD16814GS Data sheet ( Hoja de datos )
| Número de pieza | UPD16814GS | |
| Descripción | MONOLITHIC DUAL H BRIDGE DRIVER CIRCUIT | |
| Fabricantes | NEC | |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16814
MONOLITHIC DUAL H BRIDGE DRIVER CIRCUIT
DESCRIPTION
The µPD16814GS is a monolithic dual H bridge driver circuit employing a power MOS FET for its driver stage. By
complementing the P channel and N channel of the output stage, the circuit current is substantially improved as
compared with that of the conventional charge pump driver.
Because the dual H bridge driver circuits at the output stage are independent of each other, this IC is ideal as the
driver circuit for a 1- to 2-phase excitation bipolar driving stepping motor for the head actuator of an FDD.
FEATURES
• Low ON resistance (sum of ON resistance of top and bottom FETs)
RON1 = 2.0 Ω TYP.
• Low current consumption: IDD = 100 µA MAX.
• Four input modes independently controlling dual H bridge drivers
• Stop and Brake modes selectable
• Surface-mount mini-mold package: 16-pin plastic SOP (300 mil)
PIN CONFIGURATION (Top View)
VM1
1A
PGND1
2A
VDD
IN1
IN3
IN2
1
2
3
4
5
6
7
8
16 NC
15 1B
14 PGND2
13 2B
12 VM2
11 SEL
10 IN4
9 DGND
ORDERING INFORMATION
Part Number
µPD16814GS
Package
16-pin plastic SOP (300 mil)
The information in this document is subject to change without notice.
Document No. S10112EJ4V0DS00 (4th edition)
Date Published August 1997 N
Printed in Japan
©
1997
1 page  
µPD16814
RECOMMENDED OPERATING CONDITIONS (TA = 25 °C)
Parameter
Supply voltage (motor block)
Supply voltage (control block)
H bridge drive currentNote
Operating temperature
Symbol
VM
VDD
IDR
TA
MIN.
4.0
4.0
0
TYP.
5.0
5.0
MAX.
6.0
6.0
±415
60
Unit
V
V
mA
°C
Note When mounted on board (100 × 100 × 1 mm, glass epoxy)
ELECTRICAL CHARACTERISTICS (Within recommended operating conditions unless otherwise specified)
Parameter
VM pin current with output transistor OFF
VDD pin current
Control pin high-level input current
Control pin low-level input current
Control pin high-level input voltage
Control pin low-level input voltage
H bridge circuit ON resistanceNote 1
RON relative accuracy
H bridge output circuit propagation delay time
H bridge output circuit propagation delay time
H bridge output circuit rise time
H bridge output circuit fall time
Symbol
IM
IDD
IIH
IIL
VIH
VIL
RON1
∆RON
∆RON
tPHL
tPLH
tTHL
tTLH
Condition
VM = 6.0 V, VDD = 6.0 V
VIN = VDD
VIN = 0 V
VM = 5 V, VDD = 5 V
Excitation direction <2>, <4>Note 2
Excitation direction <1>, <3>
VM = 5 V, VDD = 5 VNote 3
TA = 25 °C, RM = 20 Ω
VM = 5 V, VDD = 5 VNote 3
TA = 25 °C, RM = 20 Ω
MIN.
3.0
–0.3
TYP. MAX. Unit
1.0 µA
0.1 mA
1.0 µA
–1.0 µA
VDD + 0.3 V
0.8 V
2.0 4.0
Ω
±5 %
±10
1.8 2.5 µs
0.2 0.65 µs
0.2 0.4 µs
0.1 0.2 µs
Notes 1. Sum of ON resistance of top and bottom transistors
2. For the excitation direction, refer to FUNCTION TABLE.
3.
IN1-IN4
IM
tPHL
tTHL
tPLH
tTLH
5
5 Page 
µPD16814
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
11
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| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet UPD16814GS.PDF ] | |
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