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PDF UPD16780 Data sheet ( Hoja de datos )
| Número de pieza | UPD16780 | |
| Descripción | 288/300 OUTPUT TFT-LCD SOURCE DRIVER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16780
288/300 OUTPUT TFT-LCD SOURCE DRIVER
DESCRIPTION
The µ PD16780 is a source driver for TFT-LCDs. The µ PD16780 corresponds only to LCD of Stripe array color
filter. The µ PD16780 is constitute a shift register which generates the sampling time, and a sample-and-hold circuit
which samples the analog voltage. There are two sample-and-hold circuits which perform sampling holding
alternately.
The application with high free degree is possible from driver operation system to LCD-TV because a high picture
quality is realized.
FEATURES
• 5.0 V Drive (Dynamic range 4.6 VP-P, VDD2 = 5.0 V)
• 288/300 Output channel
• fMAX. = 20 MHz (VDD1 = 3.0 V)
• Corresponds only to LCD of Stripe array color filter
• Two on-chip sample-and-hold circuits
• Small output deviation between pins (deviation between chip pins: ±20 mV MAX.)
• Switch between right and left shift using the R,/L pin
ORDERING INFORMATION
Part Number
µ PD16780N-xxx
Package
TCP (TAB package)
Remark The TCP’s external shape is custom-order item. Users are requested to consult wiht a NEC sales
representative.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S12608EJ1V0DS00 (1st edition)
Date Published May 1999 NS CP(K)
Printed in Japan
The mark • shows major revised points.
©
1998
1 page  
µ PD16780
Cautions 1. To prevent latch-up-breakdown, the power should be turned on in order VDD1, Logic input VDD2,
video signal input. It should be turned off in the opposite order. This relationship should be
followed during transition periods as well.
2. The sampling of the video signal of this IC is only the simultaneous 3 output sampling of C1, C2,
C3. Incidentally, it is designing abound of the input of the video signal in 10 MHz MAX.
If a video signal with a higher frequency is input, the data may not be correctly displayed.
3. Insert a capacitor of 0.1 µ F between VDD1 and VSS1, and VDD2 and VSS2. Unless the power supply
is reinforced, the supply voltage may fluctuate, making the sampling voltage abnormal.
4. If noise is superimposed on the start pulse pin, the data may not be displayed. For this reason,
be sure to input CX signal during the vertical blanking period.
5. If the start pulse width is extended by half the clock or longer, the sampling start timing SHP1
does not change from normal timing; therefore, the sampling operation is performed normally.
Data Sheet S12608EJ1V0DS00
5
5 Page 
CLK
STHR
(1st Dr.)
PWCLK
PWCLK(H)
PWCLK(L)
0 123
tsetup
thold
100 101 102
C1 to C3
STHL
(1st Dr.)
INVALID
S1 to S3
S4 to S6
S7 to
S9
S295 to
S297
S298 to
S300
S301 to
S303
tPLH1
tPHL1
STHL
(4th Dr.)
CX
VOUT
tCLKstop : It is possible for the clock among this to stop.
399 400 401
012
VDD1
VSS1
S1195 to
S1197
S1198 to
S1200
tSTH-CX
INVALID
tPLH1
tPHL1
tCXhold
tCXsetup
tPLH3
tPLH2
S1 to S3
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
VDD1
VSS1
tPHL2
tPHL3
Target Voltage ± 0.1 VDD1
Target Voltage ± 20 mV
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet UPD16780.PDF ] | |
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