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PDF UPD16700 Data sheet ( Hoja de datos )
| Número de pieza | UPD16700 | |
| Descripción | 256-OUTPUT TFT-LCD GATE DRIVER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16700
256-OUTPUT TFT-LCD GATE DRIVER
DESCRIPTION
The µ PD16700 is a TFT-LCD gate driver equipped with 256-output lines. It can output a high-gate scanning
voltage in response to CMOS level input because it provided with a level-shift circuit inside the IC circuit. It can also
drive the XGA/SXGA panel.
FEATURES
• CMOS level input (3.3 V)
• 256 outputs
• High-output voltage (VDD2-VEE2 = amplitude: 40 V MAX.)
• Capable of All-on outputting (AO)
ORDERING INFORMATION
Part Number
µ PD16700N-xxx
Package
TCP (TAB package)
Remark The TCP’s external shape is customized. To order the required shape, please contact an one of our sales
representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14085EJ1V1DS00 (1st edition)
Date Published July 2000 NS CP (K)
Printed in Japan
The mark • shows major revised points.
©
1999
1 page  
• 4. TIMING CHART (R,/L = H, AO = H)
CLK
12
3
OE1
OE2
OE3
STVR
(STVL)
O1
(O256)
O2
(O255)
O3
(O254)
O255
(O2)
O256
(O1)
STVL
(STVR)
O1 of next stage
(O256 of next stage)
O2 of next stage
(O255 of next stage)
µ PD16700
255 256 257 258 259
Data Sheet S14085EJ1V1DS00
5
5 Page 
µ PD16700
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S14085EJ1V1DS00
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet UPD16700.PDF ] | |
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