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PDF PCF5083 Data sheet ( Hoja de datos )
| Número de pieza | PCF5083 | |
| Descripción | GSM signal processing IC | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
DATA SHEET
PCF5083
GSM signal processing IC
Objective specification
File under Integrated Circuits, IC17
1996 Oct 29
1 page  
Philips Semiconductors
GSM signal processing IC
6 PINNING INFORMATION
6.1 Pinning
handbook, full pagewidth
TCE
PIO1
PIO2
PIO3
PIO4
PIO5
BEN
TXON
RXON
VSS1
VDD1
PDRX1
PDRX2
PDTX1
NPDTX1
VDD2
VSS2
NPDTX2
PDBIAS
NPDBIAS
PDSYN
TXKEY1
TXKEY2
DSPEN
TIMEN
RSTC
RSTO
VDD1
CLK32O
CLK32I
VSS1
ONKEY
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PCF5083
Objective specification
PCF5083
96 HD1
95 HD0
94 HA6
93 HA5
92 HA4
91 HA3
90 HA2
89 HA1
88 HA0
87 IO4/DTX
86 IO3/IRQN2
85 IO2
84 IO1/AEN
83 HCEN_T
82 TCK
81 VSS2
80 VDD2
79 TRSTN
78 TCKIO
77 TDO
76 TDI
75 TMS
74 VDDPLL
73 CKI
72 VDD1
71 VSS1
70 CKO
69 VSSPLL
68 CLKSEL
67 RSTP
66 DCLK
65 REFON
MGE282
1996 Oct 29
Fig.2 Pin configuration - PCF5083-2B and PCF5083-2C.
5
5 Page 
Philips Semiconductors
GSM signal processing IC
Objective specification
PCF5083
7 OVERVIEW OF THE GSM CHIP SET
7.1 General
The chip set’s high-level architectural modularity ensures
that it can be easily adapted to meet various market
requirements in terms of hardware and software. Figure 4
is a simplified block diagram of a GSM terminal using the
Philips Semiconductors chip set.
The receiver converts the antenna input signal from
890 to 915 MHz down into a complex baseband signal
consisting of an in-phase (I) and a quadrature
component (Q). In order to deal with the high dynamic
range from −104 to −10 dBm, the receiver provides an
AGC input controlled by the layer 1 software in the System
Controller. The complex baseband signal is connected to
the input of the PCF5072 baseband interface IC. This IC
samples the I and Q components at the GSM bit clock
(270 kHz) with an accuracy of approximately 2 × 13 bits.
The equalizer is responsible for the following tasks:
• Channel impulse response estimation and bit
synchronization by means of the training sequence
• Adaptive channel equalization with a modified Maximum
Likelihood Sequence Estimation (MLSE) approach that
produces a bit-by-bit soft decision information (Channel
Measurement Information (CMI)
• Channel impulse response adaption and frequency
offset estimation.
After decryption the channel decoder performs
convolutional and block decoding. Depending on the
logical channel in use, there are decoding schemes for
TCH/F (FACCH/F), SACCH and SDCCH.
The speech decoder synthesises the audio signal from the
received bit stream. Updating of comfort noise parameters
occurs each time a valid Silence Descriptor (SID) is
received. Comfort noise is inserted during periods of
speech pauses. Substitution and muting of lost or bad
frames is implemented.
The full rate speech encoder collects speech samples of
13-bit uniform PCM format (104 kbits/s) and compresses
them to 13 kbits/s according to the linear predictive coding,
long term prediction, Regular Pulse Excitation (RPE-LTP).
Discontinuous Transmission (DTX) is available (voice
activity detection, background acoustic noise).
To protect the data from transmission errors, block and
convolutional coders form the channel encoder. The
encoding modules relates to the logical channels (e.g.
RACH, TCH/F (FACCH/F), SDCCH/SACCH).
After encryption the burst builder generates either Normal
Bursts (NB) or Access Bursts (AB). The bit-stream is then
modulated with a GMSK modulator (Gaussian Minimum
Shift Keying) and upconverted in a quadrature mixer to
890 to 915 MHz.
The on-chip GSM timer generates all power-down and
control signals for the receiver, the transmitter, the
P90CL301 System Controller and the PCF5072 baseband
interface IC.
The System Controller (P90CL301) services all HW
interfaces and performs the signalling software contained
in the GSM layer stack (with L1, L2, L3, O&M, UAP,
SIMAP etc).
The voiceband ADCs and DACs of the PCF5072 perform
the conversion between the analog audio signals and the
digital domain.
7.2 The role of the PCF5083
The PCF5083 is a dedicated VLSI circuit offering
baseband signal processing tasks for the Pan European
Global System for Mobile telecommunication (GSM). The
PCF5083 can be applied in GSM mobile stations or
hand-helds. The embedded DSP core is optimized for
GSM baseband functions and contains an on-chip
program ROM featuring the following tasks:
• Full rate speech coding/decoding including VAD/DTX
(“GSM 06 series” )
• Encryption/decryption according to both A5/1 and A5/2
algorithms (“GSM Rec. 3.20, 3.21” )
• Burst building supporting access burst and normal burst
(“GSM Rec. 5.02”)
• Frequency Correction Burst (FCB) detection and
evaluation
• Synchronization burst (SCH) detection
• BCCH monitoring of neighbouring cells
• Channel coding/decoding and
interleaving/de-interleaving (“GSM Rec. 5.03”) for:
– Broadcast Channels (BCH): SCH, BCCH
– Common Control Channels (CCCH): PCH, RACH,
AGCH
– Dedicated Control Channels (DCH): SDCCH,
SACCH
– Traffic Channels (TCH): TCH/FS, TCH/F2.4,
TCH/F4.8, TCH/F9.6, TCH/H4.8 and TCH/H2.4
– Associated Control Channels (ACCH): FACCH and
SACCH
1996 Oct 29
11
11 Page | ||
| Páginas | Total 70 Páginas | |
| PDF Descargar | [ Datasheet PCF5083.PDF ] | |
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