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PDF UPD16662N-051 Data sheet ( Hoja de datos )

Número de pieza UPD16662N-051
Descripción 240 OUTPUT LCD COLUMN SEGMENT DRIVER WITH BUILT-IN RAM
Fabricantes NEC 
Logotipo NEC Logotipo



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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16662
240 OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH BUILT-IN RAM
The µPD16662 is a column (segment) driver which contains a RAM capable of full dot LCD drive.
With 240 outputs, this driver has a display RAM of 240 x 160 x 2 bits built in, and 4 gray scales of display are
possible. Any 4 gray scales can be selected from 25 levels of the gray scale pallet. The driver can be combined
with the µPD16667 to display from 240 x 160 dots to 480 x 320 dots.
Features
Display RAM incorporated: 240 x 160 x 2 bits
Logic voltage: 3.0V to 3.6V
Duty: 1/160
Output count: 240 outputs
Capable of gray scale display: 4 gray scales (can be selected from 25 levels of the gray scale pallet)
Memory management: packed pixel system
8/16-bit data base
Ordering Information
Part number
Package
µPD16662N -××× TCP(TAB)
µPD16662N - 051 Standard TCP (OLB: 0.2 mm pitch; folding)
The TCP’s external shape is custom-ordered. Therefore, if you have a shape in mind, please contact an NEC
salesperson.
The information in this document is subject to change without notice.
Document No. S12738EJ3V0DS00 (3rd edition)
Date Published November 1998 NS CP (K)
Printed in Japan
The mark shows major revised points.
©
1998

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UPD16662N-051 pdf
µPD16662
(12) Level shifter
The level shifter converts from the operating voltage (3.3 V) of the internal circuit to the liquid-crystal drive circuit
and low driver interface voltage (5 V).
(13) DEC
Decodes the gray scale display data to make it compatible with the liquid-crystal drive voltages V0, V1 and V2 .
(14) Liquid crystal drive circuit
This circuit selects one of the liquid-crystal drive powers V0, V1, and V2, which are compatible with the gray scale
display data and the display OFF signal (/DOFF), to generate the liquid crystal applied voltage.
(15) Self diagnostic circuit
If the operation timing of the master chip and slave chip has deviated due to external noise, this circuit will detect
the problem and generate a total column/driver refresh signal.
Address map image diagram (Example of VGA-half size configuration)
Column direction specified with A7 to A0
Row direction
specified with
A16 to A8
Y1
L1
Y240 Y1
Address progress direction
Y240
L160
No.0
No.2
L1
Address progress direction
No.1
L160
Y240
No.3
Y1 Y240
Y1
5

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UPD16662N-051 arduino
µPD16662
LSI arrangement and address management
Addresses can be managed to allow up to four of these LSIs to be used to configure a liquid-crystal display of up to
half VGA size (320 x 480 dots). Up to four of these LSIs can be connected on the same bus sharing the /CS, /WE,
and /OE pins. On the system side, one screen of the liquid crystal display can be treated as one memory area, and it
is not necessary to decode for more than one µPD16662. The PL0 and PL1 pins are used to specify LSI No. and to
determine the LSI arrangement. The DIR pins are used to determine the directions (vertical, horizontal) of the liquid-
crystal display.
PL1 PL0 LSI No.
0 0 No. 0
0 1 No. 1
1 0 No. 2
1 1 No. 3
1. Addresses of the VGA half-size horizontally (DIR = "0")
Specified
with
A16 to A8
Specified with A7 to A0
Column
Column
Y1
X1 00000
00100
00002
00038
Y240 Y1
0003A 0003C
0013A 0013C
0003E
00074
Y240
00076
00176
Row
No.0
No.2
09E00
X160 09F00
X1 0A000
0A100
09F02
0A002
09F38
0A038
09E3A
09F3A
0A03A
0A13A
09E3C
09F3C
0A03C
0A13C
09F3E
0A03E
09F74
0A074
09E76
09F76
0A076
0A176
Row
No.1
No.3
13E00
X160 13F00
Y240
13F02
13F38
13E3A 13E3C
13F3A 13F3C
Y1 Y240
13F3E
13F74
13E76
13F76
Y1
Column
Column
11

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