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PDF UPD16655N Data sheet ( Hoja de datos )
| Número de pieza | UPD16655N | |
| Descripción | 240-OUTPUT TFT-LCD GATE DRIVER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16655
240-OUTPUT TFT-LCD GATE DRIVER
The µ PD16655 is a TFT-LCD gate driver equipped with 240-output lines. It can output a high-gate scanning
voltage in response to 5 V/3.3 V CMOS level input because it provided with a level-shift circuit as a logic-input circuit.
This gate driver is also provided with an output enable (OE) function, so that drivers can be installed at both sides.
FEATURES
• High-output voltage (VDD-VEE = amplitude: 31 V MAX.)
• Shift-direction select function
• Level shift of negative voltage VEE2(level shift range: VDD-VEE2 = 15 V)
• 5 V/3.3 V CMOS level interface
• Output enable function
• As many as 240-output lines
• Slim TCP
ORDERING INFORMATION
Part Number
µ PD16655N-xxx
Package
TCP(TAB package)
Remark The TCP’s external shape is custom model. To order your TCP’s external shape, please contact a NEC
salesperson.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S11950EJ2V0DS00 (2nd edition)
Date Published February 1999 NS CP(K)
Printed in Japan
The mark shows major revised points.
© 1998
1 page  
µ PD16655
3. In an application where the VEE power supply is not shifted, short-circuit VEE2 (driver power) and VEE1
(logic power) outside the TCP. Fix unused pins to the VEE level.
4. The level shift range of VEE2 must be VEE1 ≤ VEE2 ≤ VDD – 15 V. Note that, in this case, the guaranteed
values of the output ON resistance and output fall time slightly change. (VDD = VDD1 = VDD2)
5. TIMING CHART
CLK
123
239 240 241 242
STVR
(STVL)
O1
O2
O3
O239
O240
STVL
(STVR)
O1 of
next stage
O2 of
next stage
Caution Do not use a sequence in which the outputs change all at once because such a sequence may
cause malfunctioning.
Data Sheet S11950EJ2V0DS00
5
5 Page 
µ PD16655
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet S11950EJ2V0DS00
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet UPD16655N.PDF ] | |
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