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PDF UPD16650N Data sheet ( Hoja de datos )
| Número de pieza | UPD16650N | |
| Descripción | 120-/128-OUTPUT TFT-LCD GATE DRIVER | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16650
120-/128-OUTPUT TFT-LCD GATE DRIVER
The µPD16650 is a TFT-LCD gate driver. Provided with a level shift circuit at the logic input, this chip can output
a high gate scan voltage for a CMOS-level input. The µPD16650 has an output change-over function for switching
from the 120-output mode to the 128-output mode, and vice versa, thereby supporting the VGA, SVGA, and XGA
panels. Its output enable function (OE) enables installing the driver on either side.
FEATURES
• Output with high dielectric strength (on/off range: VDD - VEE1 = 40 VMAX.)
• Built-in shift direction change-over function
• Shiftable negative supply voltage (VEE1) level (shift range: |VEE1 - VEE2| = 10 V)
• Two acceptable CMOS input levels (3.3 and 5 V)
• Output enable function
• MC-selectable output count (MC = high: 120-output mode)
(MC = low : 128-output mode)
• Slim TCP
ORDERING INFORMATION
Part number
µPD16650N-×××
µPD16650N-×××
Package
TCP (TAB package)
Standard TCP (OL pitch = 220 µm)
Remark When ordering, the customer can specify the external form of the TCP. Call one of our sales representatives
for more information.
Document No. S11041EJ1V0DS00 (1st edition)
(Previous No. IP-3677)
Date Published December 1995 P
Printed in Japan
© 1995
1 page  
µPD16650
CAUTIONS FOR USE
1) Power-on sequence
To prevent latch-up disruption, the power must be switched on in the order:
VCC → VEE1 → VEE2 → VDD → Logic input
When witching off, reverse the order. This order must be observed also during transition.
2) Insertion of bypass capacitors
The internal logic circuit operates at a high voltage. To make VIH and VIL immune to noise, use capacitors of
0.1 µF or so between supply voltages as shown below.
VDD
VCC
0.1µ F
0.1µ F
VSS
VEE2
0.1µ F
3) Negative voltage level shift
If it is necessary to shift the level of a negative supply voltage, shift the VEE1 (driver supply voltage) level. The
shift should be limited to within: VEE2 ≤ VEE1 ≤ VEE2 + 10 V
Note that shifting the VEE1 level results in the ON-state output resistance and output fall time ratings being
changed.
4) Handling the VEE1 and VEE2 driver negative supply voltage pins
For applications in which a negative supply voltage level is not shifted, connect the VEE1 pin (driver supply voltage)
to the VEE2 pin (logic supply voltage) outside the TCP. Fix all unused input pins to the VEE2 level.
5
5 Page 
µPD16650
RECOMMENDED MOUNTING CONDITIONS
When mounting this product, please make sure that the following recommended conditions are satisfied.
For packaging methods and conditions other than those recommended below, please contact NEC sales
personnel.
µPD16650N-×××
Mounting Condition
Mounting Method
Condition
Thermocompression Soldering
Heating tool 300 to 350 ˚C; heating for 2 to 3 seconds; pressure 100 g
(per solder)
ACF (Sheet-shape bonding
agent)
Temporary bonding 70 to 100 ˚C; pressure 3 to 8 kg/cm2; time 3 to 5
secs.
Real bonding 165 to 180 ˚C; pressure 25 to 45 kg/cm2; time 30 to 40
secs. (when using the anisotropic conductive film SUMIZAC1003 of
Sumitomo Bakelite, Ltd.)
Caution To find out the detailed conditions for packaging the ACF part, please contact the ACF
manufacturing company. Be sure to avoid using two or more packaging methods at a time.
Reference
NEC Semiconductor Device Reliability/Quality Control System (IEI-1212)
Quality Grades to NEC’s Semiconductor Devices (IEI-1209)
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet UPD16650N.PDF ] | |
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