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PDF UPD16647 Data sheet ( Hoja de datos )

Número de pieza UPD16647
Descripción 402/384-OUTPUT TFT-LCD SOURCE DRIVER 64 GRAY SCALE
Fabricantes NEC 
Logotipo NEC Logotipo



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DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16647
402/384-OUTPUT TFT-LCD SOURCE DRIVER (64 GRAY SCALE)
DESCRIPTION
The µ PD16647 is a source driver for TFT-LCD 64 gray scale displays. Its logic circuit operates at 3.3 V and the
driver circuit operates at 5.0 V. The input data is digital data at 6 bits x 3 dots, and 260,000 colors can be displayed
in 64-value outputs γ -corrected by the internal D/A converter and 10 external power supplies. The clock frequency is
50 MHz MIN. µ PD16647 can be used in TFT-LCD panels conforming to the SVGA standards.
FEATURES
CMOS level input
402/384 outputs
6 bits (gray scale data) x 3 dots input
64-value output by 10 external power supplies and internal D/A converter
Output dynamic range : VSS2 + 0.1 V to VDD2 0.1 V
High-speed data transfer: fMAX =50 MHz MIN.(internal data transfer rate at supply voltage VDD1 of logic circuit =3.0 V)
Level of γ -corrected power supply can be inverted
Input data inversion function (INV)
Precharge-less output buffer
Logic supply voltage (VDD1) : 3.3 V ± 0.3 V
Driver supply voltage (VDD2) : 5.0 V ± 0.5 V
Slim TCP
ORDERING INFORMATION
Part Number
Package
µ PD16647N-xxx
TCP (TAB package)
Remark The TCP package is a custom-ordered item. Users are requested to consult with an NEC sales
representative.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S13607EJ2V0DS00 (2nd edition)
Date Published August 1999 NS CP (K)
Printed in Japan
The mark shows major revised points.
©
1998

1 page




UPD16647 pdf
µ PD16647
4. RELATION BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE
The 10 major points on the γ -characteristic curve of the LCD panel are arbitrarily set by external power supplies V0
through V9. If the display data is 00H or 3FH, gray scale voltage V0 or V9 is output. If the display data is in the range
01H to 3EH, the high-order 3 bits select an external power pair Vn+1, Vn. The low-order 3 bits evenly divide the range
of Vn+1 to Vn into eight segments by means of D/A conversion (however, the ranges from V8 to V7 and from V1 to V0
are divided into seven segments) to output a 64 gray scale voltage.
DX5(MSB)
DX4
DX3 DX2 DX1 DX0 (LSB)
High-order 3 bits
: γ-corrected power selected
(Vn, Vn+1)
Low-order 3 bits
: 3-bit D/A (range Vn to Vn+1 is divided to 7 or 8 segments)
DX5
DX4
DX3
000
001
010
011
100
101
110
111
Vn+1-Vn
V1-V2
V2-V3
V3-V4
V4-V5
V5-V6
V6-V7
V7-V8
V8-V9
Vn 1
2
3
4
5
6
7
8
Vn+1
000 001 010 011 100 101 110 111
VDD2 V0
Figure4-1. Relationship between Input Data and γ-corrected Voltage
gray scale supply specified
by 00H
7 segments
V1
8 segments
V2
8 segments
V3
8 segments
V4
8 segments
V5
8 segments
V6
8 segments
V7
7 segments
V8
VSS2 V9
gray scale supply specified
0 7 F 17 1F 27 2F 37 3F by 3FH
Input data (HEX)
Data Sheet S13607EJ2V0DS00
5

5 Page





UPD16647 arduino
µ PD16647
Electrical Characteristics (TA = –10 to +75 °C, VDD1 = 3.3 V ± 0.3 V, VDD2 = 5.0 V ± 0.5 V, VSS1 = VSS2 = 0 V)
Parameter
Symbol
Condition
MIN.
Input Leakage Current
Pull-up Resistor
High-level Output Voltage
Low-level Output Voltage
Static Current Consumption of
γ -corrected Power
IIL
RPU
VOH
VOL
Ivn1
Driver Output Current
IVOH2
IVOL2
Output Voltage Deviation
VO
Output Swing Difference Deviation
VP-P
Output Voltage Range
VO
Dynamic Logic Current Consumption IDD1
Dynamic Driver Current Consumption IDD2
D00-D05,D10-D15,D20-D25
R,/L,STB
VDD1 = 3.3 V
40
STHR(STHL),IO = 1.0 mA
VDD1 0.5
STHR(STHL),IO = +1.0 mA
VDD1 = 3.3 V,
V0-V1
126
Vn Vn+1 = 0.5 V, V1-V2
145
VDD2 = 5.0 V
V2-V3
289
V3-V4
252
V4-V5
343
V5-V6
315
V6-V7
237
V7-V8
158
V8-V9
VOUT = 4.4 V, VX = 4.9 V Note1
VDD1 = 3.3 V, VDD2 = 5.0 V
VOUT = 0.6 V, VX = 0.1 V Note1
VDD1 = 3.3 V, VDD2 = 5.0 V
40
(0.12)
0.04
VDD1 = 3.3 V, VDD2=5.0 V,
VOUT=2.5 V Note1
Input data
Input data : 00H to 3FH
No load, VDD2 = 3.3 V Note2
No load, VDD2 = 5.0 V Note2
VSS2 + 0.1
TYP.
100
253
291
579
504
686
631
474
316
80
±10
(±5)
0.5
5.0
MAX.
±1.0
250
0.5
506
582
1158
1008
1372
1262
948
632
160
0.03
(0.16)
±20
VDD2 0.1
2.5
10.0
Unit
µA
k
V
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mV
mV
V
mA
mA
Notes 1. VX refers to the output voltage of analog output pins S1 to S402/384.
VOUT refers to the voltage applied to analog output pins S1 to S402/384.
2. The STB cycle is specified at 31 µ s and fCLK= 16 MHz.
Data Sheet S13607EJ2V0DS00
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