|
|
PDF UPD16634A Data sheet ( Hoja de datos )
| Número de pieza | UPD16634A | |
| Descripción | 300-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 64 GRAY SCALE | |
| Fabricantes | NEC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de UPD16634A (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16634A
300-OUTPUT TFT-LCD SOURCE DRIVER
(COMPATIBLE WITH 64 GRAY SCALE)
DESCRIPTION
The µPD16634A is a source driver for TFT-LCDs capable of dealing with displays 64 gray scales. Data input is
based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors
by output of 64 values γ -corrected by an internal D/A converter and 5-by-2 external power modules. Because the
5 output dynamic range is as large as VSS2+0.1 V to VDD2−0.1 V, level inversion operation of the LCD’s common
electrode is rendered unnecessary. Also to be able to deal with dot-line inversion when mounted on a single side,
this source driver equipped with a built-in 6-bit D/A converter circuit whose odd output pins and even output pins
respectively output gray scale voltages of differing polarity. Assuring a maximum clock frequent of 40 MHz when
drivng at 3.0 V, this driver is applicable to XGA-standard TFT-LCD panels.
FEATURES
• 300 outputs
• CMOS level input
• Input of 6 bits (gradation data) by 6 dots
• Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter
5 • Output dynamic range : VSS2+0.1 V to VDD2−0.1 V
5 • Logic part supply voltage (VDD1) : 3.3 V ± 0.3 V
5 • Driver part supply voltage (VDD2) : 8.0 V ± 0.5 V
• High-speed data transfer: fMAX=40 MHz MIN.(internal data transfer rate when operating at 3.0 V)
• Output voltage polarity inversion is possible (POL)
• Display data inversion function (POL2)
• Single bank arrangement is possible(loaded with slim TCP).
ORDERING INFORMATION
Part Number
µPD16634AN-xxx
Package
TCP (TAB package)
Remark The TCP’s external shape is customized. To order your TCP’s external shape, please contact a NEC
salesperson.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S12595EJ2V0DS00 (2nd edition)
Date Published March 1999 NS CP (K)
Printed in Japan
The mark • shows major revised points.
©
1998
1 page  
µPD16634A
4. PIN FUNCTIONS
Pin Symbol
Pin Name
Description
S1 to S300
Driver output
The D/A converted 64-gray-scale analog voltage is output
D00 to D05
Display data input
The display data is input with a width of 36 bits, viz., the gray scale data
D10 to D15
(6 bits) by 6 dots (2 pixels).
D20 to D25
DX0 : LSB, DX5 : MSB
D30 to D35
D40 to D45
D50 to D55
R,/L
STHR
STHL
Shift direction switching input
Right shift start pulse
input/output
Left shift start pulse input/output
These refer to the start pulse input/output pins when cascades are
connected. The shift directions of the shift registers are as follows.
R,/L = H : STHR input, S1→S300, STHL output
R,/L = L : STHL input, S300→S1, STHR output
R,/L = H : Becomes the start pulse input pin.
R,/L = L : Becomes the start pulse output pin.
R,/L = H : Becomes the start pulse input pin.
R,/L = L : Becomes the start pulse output pin.
CLK
Shift clock input
Refers to the shift register’s shift clock input. The display data is
incorporated into the data register at the rising edge. At the rising edge of
the 50th clock after the start pulse input, the start pulse output reaches the
high level, thus becoming the start pulse of the next-level driver. The initial-
level driver’s 50th clock becomes valid as the next-level driver’s start pulse
is input. If 52 clock pulses are input after input of the start pulse, input of
display data is halted automatically. The contents of the shift register are
cleared at the STB’s rising edge.
STB
POL
Latch input
Polarity input
The contents of the data register are transferred to the latch at the rising
edge. And, at the falling edge, the gray scale voltage is supplied to the
driver. It is necessary to ensure input of one pulse per horizontal period.
POL = L ; The S2n-1 output uses V0 to V4 as the reference supply; and the S2n
output uses V5 to V9 as the reference supply.
POL = H ; The S2n-1 output uses V5 to V9 as the reference supply; and the
S2n output uses V0 to V4 as the reference supply.
S2n-1 indicates the odd output; and S2n indicates the even output. Input of
the POL signal is allowed the setup time (tPOL-STB) with respect to STB’s
rising edge.
POL2
V0 to V9
Data inversion input
γ-corrected power supplies
TEST
Test pin
POL2 = H : Display data is inverted.
POL2 = L : Display data is not inverted.
Input the γ-corrected power supplies from outside by using operational
amplifier. Make sure to maintain the following relationships. During the gray
scale voltage output, be sure to keep the gray scale level power supply at a
constant level.
VDD2 > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2
Set it to open.
VDD1
Logic circuit power supply
3.3 V ± 0.3 V
VDD2
Driver circuit power supply
8.0 V ± 0.5 V
VSS1
Logic ground
Grounding
VSS2
Driver ground
Grounding
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse
this sequence to shut down.(Simultaneous power application to VDD2 and V0 to V9 is possible.)
2. To stabilize the supply voltage, please be sure to insert 0.1 µF bypass capacitor between
VDD1-VSS1 and VDD2-VSS2. Furthermore, for increase precision of the D/A converter, insertion of a
bypass capacitor of about 0.01 µF is also advised between the γ-corrected power supply
terminals(V0,V1,V2...,V9) and VSS2.
3. We recommend to use Operational Amplifier to lower input impedance of γ-corrected voltage.
Data Sheet S12595EJ2V0DS00
5
5 Page 
µPD16634A
9. CAUTIONS ABOUT FRAME INVERSION
In the case of dot inversion, n frame last line and (n+1) frame first line is the same polarity. When write the same
polarity twice; there are two cases as follows.
(1) Last line output in n frame > First line output in (n+1) frame → Positive to write
(2) Last line output in n frame < First line output in (n+1) frame → Not possible to write
µPD16634A has charge buffer and discharge buffer, so need to inversion polarity and write in the case of both
ways.
STB
POL
n frame last line
Discharge buffer
Vertical intervals
(n+1) frame
first line
(n+1) frame
second line
Charge buffer
S2N
VCOM
Hi-Z Hi-Z Hi-Z
STB
POL
S2N
n frame last line
Vertical intervals
(n+1) frame
first line
(n+1) frame
second line
Hi-Z Hi-Z Hi-Z
VCOM
Hi-Z
Data Sheet S12595EJ2V0DS00
11
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet UPD16634A.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| UPD16634A | 300-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 64 GRAY SCALE | NEC |
| UPD16634AN | 300-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 64 GRAY SCALE | NEC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |