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PDF UPD16520 Data sheet ( Hoja de datos )
| Número de pieza | UPD16520 | |
| Descripción | VERTICAL DRIVER FOR CCD SENSORS | |
| Fabricantes | NEC | |
| Logotipo |  |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16520
VERTICAL DRIVER FOR CCD SENSORS
The µPD16520 is a vertical driver for CCD image sensors that has a level conversion circuit and a 3-level output
function. Since it incorporates a CCD vertical register driver equivalent to the µPD16510 (10 channels, consisting of
six 3-level channels and four 2-level channels) and a VOD shutter driver (1 channel), it is ideal as a vertical driver for
multiple-electrode high-pixel CCD transfer type area image sensors employed in digital still cameras.
The µPD16520 uses a CMOS process to achieve optimum transmission delay characteristics for vertical driving of
CCD image sensors, as well as output on-state resistance characteristics. The µPD16520 also supports low-voltage
logic (logic supply voltage: 2.0 to 5.5 V).
FEATURES
• CCD vertical register driver: 10 channels (3-level: 6 channels, 2-level: 4 channels)
• VOD shutter driver: 1 channel
• High withstand voltage: 33 V Max.
• Low-output on-state resistance: 30 Ω TYP.
• Low-voltage input supported (Logic supply voltage: 2.0 to 5.5 V)
• Latch-up free
• Same drive capacity as µPD16510
• Small package: 38-pin plastic shrink SOP (300 mil)
APPLICATIONS
Digital still cameras, digital video cameras, etc.
ORDERING INFORMATION
Part Number
Package
µPD16520GS-BGG
38-pin plastic shrink SOP (300 mil)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S14201EJ1V0DS00 (1st edition)
Date Published May 1999 N CP(K)
Printed in Japan
©
1999
1 page  
µPD16520
Function Tables
VL = VSS, VMa = VDD2a, VMb = VDD2b, VH = VDD1, VHH = Vsb
Pins TO1 to TO6
Pin Name
Pin No.
Input
Output
TI1 TI2 TI3 TI4 TI5 TI6 PG1 PG2 PG3 PG4 PG5 PG6 TO1 TO2 TO3 TO4 TO5 TO6
3 4 5 6 7 8 9 10 11 12 13 14 36 34 33 31 30 28
L L VH
L H VMa
HL
VL
HH
VL
Pins BO1 to BO4
Input
Output
Pin Name BI1 BI2 BI3 BI4 BO1 BO2 BO3 BO4
Pin No.
15 16 17 18
27
26
24
23
L VMb
H VL
Pin SUBO
Pin Name
Pin No.
Input
SUBI
19
L
H
Output
SUBO
22
VHH
VL
Data Sheet S14201EJ1V0DS00
5
5 Page 
µPD16520
(2) Power OFF
<1> Powering OFF Vsb, VDD1, VDD2a, VDD2b, VSS
Until VCC power OFF, keep SUBI high level (0.8VCC or higher).
<2> Powering OFF VCC
Power OFF VCC when Vsb becomes 2 V or lower. At this time, make sure that the input pin voltage (TI1 to
TI6, PG1 to PG6, BI1 to BI4, SUBI) ≤ VCC.
Vsb
VDD1
<1>
Vcc
VDD2a, VDD2b
Vss
<2>
2V
0V
Time
3.2. Recommended Connection of Unused Pins
Handle input pins and output pins that are not used as follows.
Input pin: High level (connect to VCC)
Output pin: Leave open
Data Sheet S14201EJ1V0DS00
11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet UPD16520.PDF ] | |
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