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PDF UPD16448A Data sheet ( Hoja de datos )

Número de pieza UPD16448A
Descripción SOURCE DRIVER FOR 240-OUTPUT TFT-LCD NAVIGATION/ AUTOMOBILE LCD-TV
Fabricantes NEC 
Logotipo NEC Logotipo



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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD16448A
SOURCE DRIVER FOR 240-OUTPUT TFT-LCD
(NAVIGATION, AUTOMOBILE LCD-TV)
µPD16448A is a source driver for TFT liquid crystal panels. This IC consists of a multiplexer circuit supporting a
variety of pixel arrays, a shift register that generates sampling timing, and two sample and hold circuits that sample
analog voltages. Because the two sample and hold circuits alternately execute sampling and holding, a high
definition can be obtained.
In addition, simultaneous sampling and successive sampling are automatically selected according to the pixel
array of the LCD panel. It is ideal for a wide range of applications, including navigation systems and automobile LCD-
TVs.
FEATURES
Can be driven on 5 V (Dynamic range: 4.3 V, VDD2 = 5.0 V)
240-output
fmax. = 18 MHz (VDD1 = 3.0 V)
Simultaneous/successive sampling selectable according to pixel array
Simultaneous sampling: vertical stripe
Successive sampling: delta array, mosaic array
Two sample and hold circuits
Low output deviation between pins (± 20 mV MAX.)
Stripe, delta, and mosaic pixel arrays supported by internal multiplexer circuit
Left and right shift selected by R/L pin
Single-side mounting possible
ORDERING INFORMATION
Part Number
µPD16448AN-×××
Package
TCP (TAB package)
Remark The dimensions of TCP are custom-made. Please consult NEC for details.
The information in this document is subject to change without notice.
Document No. S11712EJ3V0DS00 (3rd edition)
Date Published August 1998 NS CP(K)
Printed in Japan
The mark 5 shows major revised points.
©
1998

1 page




UPD16448A pdf
µPD16448A
2. FUNCTION DESCRIPTION
2.1 Multiplexer Circuit
This circuit selects RGB video signals input to the C1, C2, and C3 pins according to the pixel array of the liquid
crystal panel, and outputs the signals to the H1 through H240 pins.
Vertical stripe array, single-/double-side delta array, or mosaic array can be selected by using the MP/TH and
MP/1.5 pins.
2.1.1 Vertical stripe array mode (MP/TH = L, MP/1.5 = L)
In this mode, the relation between video signals C1, C2, and C3, and output pins is as shown below. This
mode is used to drive a panel of vertical stripe array. In this mode, the multiplexer circuit is in the through
status.
Relation between video signals C1, C2, and C3, and output pins (during right shift)
Line No.
(number of
INHs)
RESET
0H
1L
2L
3L
::
::
INH
H1 (H240)
H2 (H239)
H3 (H238)
H4 (H237)
H239 (H2)
H240 (H1)
Sampling Sampling Sampling Sampling
Sampling Sampling
L
C1 (C3)
C2 (C2)
C3 (C1)
C1 (C3)
C2 (C2)
C3 (C1)
Output
Output
Output
Output
Output
Output
C1 (C3)
C2 (C2)
C3 (C1)
C1 (C3)
C2 (C2)
C3 (C1)
Output
Output
Output
Output
Output
Output
C1 (C3)
C2 (C2)
C3 (C1)
C1 (C3)
C2 (C2)
C3 (C1)
Output
Output
Output
Output
Output
Output
C1 (C3)
C2 (C2)
C3 (C1)
C1 (C3)
C2 (C2)
C3 (C1)
:::::
:::::
::
::
( ) indicates the case of left shift.
Pixel arrangement of vertical stripe array and multiplexer operation
R C1
B C2
G C3
µ PD16448A
H1 H2
Right shift (R/L = "H"), MP/TH = "L", MP/1.5 = "L"
H3 H4 H5 H6 H7
RBGRBGR
RBGRBGR
RBGRBGR
RBGRBGR
RBGRBGR
5

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UPD16448A arduino
µPD16448A
2.1.4 Mosaic array mode (MP/TH = H, MP/1.5 = L)
Relation between video signals C1, C2, and C3, and output pins
Line No.
(number of
INHs)
RESET
0H
1L
2L
3L
4L
5L
::
::
INH
H1 (H240)
H2 (H239)
H3 (H238)
H4 (H237)
H239 (H2)
H240 (H1)
L Undefined Undefined Undefined Undefined Undefined Undefined
Sampling Sampling Sampling Sampling
Sampling Sampling
C1 (C3)
C2 (C2)
C3 (C1)
C1 (C3)
C2 (C2)
C3 (C1)
Output
Output
Output
Output
Output
Output
C1 (C3)
C2 (C2)
C3 (C1)
C1 (C3)
C2 (C2)
C3 (C1)
Output
Output
Output
Output
Output
Output
C3 (C2)
C1 (C1)
C2 (C3)
C3 (C2)
C1 (C1)
C2 (C3)
Output
Output
Output
Output
Output
Output
C2 (C1)
C3 (C3)
C1 (C2)
C2 (C1)
C3 (C3)
C1 (C2)
Output
Output
Output
Output
Output
Output
C1 (C3)
C2 (C2)
C3 (C1)
C1 (C3)
C2 (C2)
C3 (C1)
:::::
:::::
::
::
( ) indicates the case of left shift.
Pixel arrangement of mosaic array and multiplexer operation
R C1
G C2
B C3
µ PD16448A
H1 H2
Right shift (R/L = "H"), MP/TH = "H", MP/1.5 = "L"
H3 H4 H5 H6 H7
RGBRGBR
BRGBRGB
GBRGBRG
RGBRGBR
BRGBRGB
11

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