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PDF UPC8195K-E1 Data sheet ( Hoja de datos )

Número de pieza UPC8195K-E1
Descripción TX-IF SiMMIC FOR W-CDMA AGC + I/Q MODULATOR
Fabricantes NEC 
Logotipo NEC Logotipo



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TX-IF SiMMIC FOR W-CDMA
AGC + I/Q MODULATOR
UPC8195K
FEATURES
• TX-IF:
380 MHz
• LOW POWER CONSUMPTION:
VCC= 3.0 V
• SMALL 20 PIN QFN PACKAGE:
Flat lead style for better performance
• TAPE AND REEL PACKAGING AVAILABLE
DESCRIPTION
The UPC8195K is a Silicon Microwave Monolithic Integrated
Circuit designed as a transmitter/TX section for W-CDMA.
The UPC8195K is a TX-IF IC including IF-AGC amplifier and
modulator. This IC is suitable for kit-use for W-CDMA IF
section.
This IC was developed using NEC's new ultra high seed
silicon bipolar process.
NEC's stringent quality assurance and test procedures en-
sure the highest reliability and perormance.
BLOCK DIAGRAM
15 14 13 12 11
16 Reg. &
AGC CTRL
17
LPF
18
19
Freq.1/2
+ Phase
20 Shifter
1 23 45
APPLICATIONS
• W-CDMA
10
9
8
7
6
ELECTRICAL CHARACTERISTICS (unless otherwise specified,TA = 25°C, VCC = 3.0 V, fIF = 380 MHz, fLO = 760 MHz,
PLO = -15 dBm, fI/Q =10 kHz, 400 mVp-p balanced sine-wave)
PART NUMBER
UP8195K
PACKAGE OUTLINE
QFN-20
SYMBOLS
PARAMETERS AND CONDITIONS
UNITS
MIN
TYP
MAX
ICC Circuit Current, no input signals
At power saving mode
mA – 25.5 30
µA –
1
POUT
Output Power, VCONT= 2.3 V, I/Q = 400mVp-p balanced
VCONT= 0.3 V, I/Q = 400mVp-p balanced
dBm
-17
-13
-88
-83
LoL Local Leakage, VCONT= 2.3 V, I/Q = 400mVp-p balanced
dBc
-30
ImR Image Rejection, VCONT= 2.3 V, I/Q = 400mVp-p balanced
dBc
-30
TPS(Rise) Rise time from power-saving mode
us – – 10
VPS(Rise) Rising voltage from power-saving mode
V 2.2
VPS(fall) Falling voltage from power-saving mode
V – – 0.5
California Eastern Laboratories

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UPC8195K-E1 pdf
PIN FUNCTIONS (Pin Voltage is measured at VCC = 2.85 V)
Applied Pin
Pin Pin Voltage Voltage
No. Name
(V)
(V)
Functions and Applications
10 Vcont 0 to 3.0
-
Gain control pin of AGC amplifier.
Variable gains are available in
accordance with applied voltage
between 0 to 3.0 V.
UPC8195K
Internal Equivalent Circuits
10.5 k
2.5 k
11 VCC 2.7 to 3.3
(REG.)
12 GND
(REG.)
0
-
-
13 GND
14 (AGC,
18 MIX)
0
-
15 VCC 2.7 to 3.3
(AGC
, MIX)
-
16 IFout 2.7 to 3.3 -
17 IFoutb 2.7 to 3.3 -
Supply voltage pin of internal regulator.
Ground pin internal regulator.
This pin should be grounded with
minimum inductance.
Form the ground pattern as widely
as possible to minimize ground impedance.
Ground pin of AGC amplifier + I/Q Mixer.
This pin should be grounded with
minimum inductance.
Form the ground pattern as widely
as possible to minimize ground impedance.
Supply voltage pin of AGC amplifier +
I/Q Mixer.
IF output pin.
The inductor must be attached between
VCC and output pin due to open collector.
Output frequency is 570 MHz which is
3/4 of local signal frequency 760 MHz.
Balance output of IFout pin.
The inductor must be attached between
VCC and output pin due to open collector.
19
I
VCC/2
-
20 Ib VCC/2 -
I signal input pin.
Apply bias voltage externally.
Maximum balance input voltage is
1 000 mVP-P (balance).
19
External
16 17
1 k
20

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