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Número de pieza | UPC1854A | |
Descripción | I2C BUS-COMPATIBLE US MTS PROCESSING LSI | |
Fabricantes | NEC | |
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No Preview Available ! DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC1854A
I2C BUS-COMPATIBLE US MTS PROCESSING LSI
The µPC1854A is an integrated circuit for US MTS (Multichannel Television Sound) system with the addition of
the I2C bus interface. All functions required for US MTS system are incorporated on a single chip.
The µPC1854A allows users to switch modes and adjust filter and separation circuits through the I2C bus.
FEATURES
• Stereo demodulation, SAP (Sub Audio Program) demodulation, dbx noise reduction decoding, and I2C bus
interface incorporated on a single chip
• Mode switching and filter/separation adjustments through the I2C bus
• Power supply: 8 V to 10 V
• On-chip input attenuator for simple interface with intermediate frequency processing IC (I2C bus control)
• Output level: 1.4 Vp-p (with L+R signals, 100% modulation)
APPLICATIONS
• TV sets and VCRs for north America
ORDERING INFORMATION
Part Number
µPC1854ACT
µPC1854AGT
Package
28-pin plastic SDIP (10.16 mm (400))
28-pin plastic SOP (9.53 mm (375))
The µPC1854A is available only to licensees of THAT Corporation.
For information, please call: (508) 229-2500 (U.S.A.), or (03) 5790-5391 (Tokyo).
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S12816EJ3V0DS00 (3rd edition)
Date Published June 2000 N CP(K)
Printed in Japan
The mark shows major revised points.
©
1997
1 page µPC1854A
CONTENTS
1. PIN EQUIVALENT CIRCUITS .............................................................................................................................. 6
2. BLOCK FUNCTIONS .......................................................................................................................................... 13
2.1 Stereo Demodulation Block ..................................................................................................................... 14
2.2 SAP Demodulation Block ........................................................................................................................ 15
2.3 dbx Noise Reduction Block ..................................................................................................................... 16
2.4 Matrix Block .............................................................................................................................................. 17
3. I2C BUS INTERFACE ......................................................................................................................................... 18
3.1 Data Transfer ........................................................................................................................................... 19
3.2 Data Transfer Format .............................................................................................................................. 20
4. I2C BUS COMMANDS ........................................................................................................................................ 22
4.1 Subaddress List ....................................................................................................................................... 22
4.2 Setting Procedure .................................................................................................................................... 23
4.3 Explanation of Write Register .................................................................................................................. 25
4.4 Explanation of Read Register ................................................................................................................. 28
5. MODE MATRIX ................................................................................................................................................... 30
5.1 L-, R-Channel Output (LOT, ROT pins) Matrix ....................................................................................... 30
5.2 Normal Output (NOT pin) Matrix ............................................................................................................. 31
6. USAGE CAUTIONS ............................................................................................................................................ 32
6.1 Caution on Shock Noise Reduction ........................................................................................................ 32
6.2 Supply Voltage ......................................................................................................................................... 32
6.3 Impedance of Input and Output Pins ...................................................................................................... 32
6.4 Drive Capability of Output Pins ............................................................................................................... 32
6.5 Caution on External Components ........................................................................................................... 33
6.6 Change of Electrical Characteristics by External Components ............................................................. 33
7. ELECTRICAL SPECIFICATIONS ...................................................................................................................... 34
8. MEASURING CIRCUIT ....................................................................................................................................... 44
9. PACKAGE DRAWINGS ..................................................................................................................................... 45
10. RECOMMENDED SOLDERING CONDITIONS ................................................................................................ 47
Data Sheet S12816EJ3V0DS00
5
5 Page µPC1854A
Pin No.
Pin Name
20 Wide-Band RMS Offset Absorption
Symbol
Internal Equivalent Circuit
WRB Same as pin 19
21 Timing Current Setting
ITI
10 kΩ 10 kΩ
(6/7)
VCC
22 Spectral RMS Timing
23 Wide-Band RMS Timing
24 VCA Offset Absorption
20 pF
5 kΩ
10 kΩ
10
kΩ
10 kΩ
10
kΩ
21
STI
30 kΩ
GND
5 kΩ
600 Ω
VCC
5 kΩ
22
5 kΩ
WTI Same as pin 22
VOA Same as pin 8
5 kΩ
5 kΩ
GND
Data Sheet S12816EJ3V0DS00
11
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet UPC1854A.PDF ] |
Número de pieza | Descripción | Fabricantes |
UPC1854A | I2C BUS-COMPATIBLE US MTS PROCESSING LSI | NEC |
UPC1854ACT | I2C BUS-COMPATIBLE US MTS PROCESSING LSI | NEC |
UPC1854AGT | I2C BUS-COMPATIBLE US MTS PROCESSING LSI | NEC |
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