PDF UPA1760 Data sheet ( Hoja de datos )

Número de pieza	UPA1760
Descripción	SWITCHING N-CHANNEL POWER MOS FET INDUSTRIAL USE
Fabricantes	NEC
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No Preview Available ! DATA SHEET MOS FIELD EFFECT TRANSISTOR µPA1760 SWITCHING N-CHANNEL POWER MOS FET INDUSTRIAL USE DESCRIPTION The µPA1760 is N-Channel MOS Field Effect Transistor designed for DC/DC Converters and power management application of notebook computers. FEATURES • Dual Chip Type • Low On-Resistance 5 RDS(on)1 = 26.0 mΩ MAX. (VGS = 10 V, ID = 4.0 A) 5 RDS(on)2 = 36.0 mΩ MAX. (VGS = 4.5 V, ID = 4.0 A) 5 RDS(on)3 = 42.0 mΩ MAX. (VGS = 4.0 V, ID = 4.0 A) • Low Ciss : Ciss = 760 pF TYP. • Built-in G-S Protection Diode • Small and Surface Mount Package (Power SOP8) PACKAGE DRAWING (Unit : mm) 85 14 5.37 Max. 1 ; Source1 2 ; Gate1 7, 8 ; Drain1 3 ; Source2 4 ; Gate2 5, 6 ; Drain2 6.0 ±0.3 4.4 0.8 1.27 0.78 Max. 0.40 +0.10 –0.05 0.12 M 0.5 ±0.2 0.10 ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, All terminals are connected.) Drain to Source Voltage (VGS = 0 V) VDSS 30 V Gate to Source Voltage (VDS = 0 V) Drain Current (DC) Drain Current (Pulse) Note1 Total Power Dissipation (1 unit) Note2 Total Power Dissipation (2 unit) Note2 VGSS ID(DC) ID(pulse) PT PT ±20 ±8.0 ±32 1.7 2.0 V A A W W EQUIVALENT CIRCUIT (1/2 Circuit) Drain Channel Temperature Storage Temperature 5 Single Avalanche Current Note3 5 Single Avalanche Energy Note3 Tch 150 °C Tstg –55 to + 150 °C IAS 8 A EAS 6.4 mJ Gate Body Diode Gate Protection Diode Source Notes 1. PW ≤ 10 µs, Duty cycle ≤ 1 % 5 2. TA = 25 °C, Mounted on ceramic substrate of 2000 mm2 x 1.6 mm 5 3. Starting Tch = 25 °C, RG = 25 Ω, VGS = 20 V → 0 V Remark The diode connected between the gate and source of the transistor serves as a protector against ESD. When this device actually used, an additional protection circuit is externally required if a voltage Exceeding the rated voltage may be applied to this device. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. G13891EJ1V0DS00 (1st edition) Date Published November 1999 NS CP(K) Printed in Japan The mark 5 shows major revised points. © 1998,1999 1 page µPA1760 DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA 100 80 60 40 20 0 20 40 60 80 100 120 140 160 TA - Ambient Temperature - ˚C TOTAL POWER DISSIPATION vs. AMBIENT TEMPERATURE 2.8 Mounted on ceramic substrate of 2.4 2000 mm2×1.6 mm 2 unit 2.0 1 unit 1.6 1.2 0.8 0.4 0 20 40 60 80 100 120 140 160 TA - Ambient Temperature - ˚C FORWARD BIAS SAFE OPERATING AREA 100 Mounted on ceramic substrate of 10 1 TARD(=VS(GonS2) =L5i1m0i˚tVIeC)Dd (DC)PowIeDr(pDuilsses)PipWati=oP1n20WL00i=0mmP10Wist0mem=dm1s2m×s1P.6Wm=m10, 01µusnit 0.1 Single Pulse 0.1 1 10 100 VDS - Drain to Source Voltage - V 1 000 100 TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH Rth(ch-A) = 73.5˚C/W 10 1 0.1 0.01100µ 1m 10 m 100 m Mounted on ceramic substrate of 2000mm2 × 1.6mm Single Pulse, 1 unit, TA=25˚C 1 10 100 1 000 PW - Pulse Width - s Data Sheet G13891EJ1V0DS00 5 5 Page

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